Abdallah Kassem

Integrated Front-End Receiver for a Portable Ultrasonic System

This paper concerns the design, the implementation and the validation of a fully integrated front-end receiver for a portable ultrasonic system. This front-end receiver includes a logarithmic preamplification circuit and followed by a programmable-gain compensator. The proposed building blocks largely amplify small amplitude signals, and moderately the large amplitude ones. They also compensate signal attenuation due to its traveling of several human body tissues. The ultrasonic receiver is implemented in CMOS 0.35 μm technology. Spectre simulations of the front-end receiver show unity gain bandwidth higher than 100 MHz when driving a load of 1 pF. The expected measurements of the fabricated chip are reported. This chip operates at 3.3 V supply voltages, while maintaining wide common mode rejection ratio, high gain and low input offset voltage. The total power consumption is 15.6 mW and the total chip area is 7.2 mm2 including the digital part needed to program the TGC.

Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers

This paper concerns the design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers. The ADC is used in the front-end stage to convert the signals coming from the time gain compensator (TGC) of the handheld ultrasonic apparatus. The proposed architecture is based on 1.5 bits per stage pipeline structure followed by a digital offset compensation to relax the constraints on the analog circuitry. The converter is implemented in digital CMOS 0.18 /spl mu/m technology, the circuit occupies an active area of 1.2 mm/sup 2/, the input differential voltage dynamic range is chosen to be 1.6 Vpp and the power consumption is found to be 31 mW from 1.8 V supply.

A NEW DIGITAL SCAN CONVERSION ARCHITECTURE FOR ULTRASONIC IMAGING SYSTEMS

Digital scan conversion (DSC) is the process of converting received ultrasound signals, or echoes, in multi-scan lines, at varying angles (polar coordinate), to a Cartesian raster format for displaying. In this paper, we propose a new DSC technique that uses nearest-neighbor interpolation and the linear interpolation between adjacent scan lines to reduce artifacts on the far field, with smaller angular separation between the interpolated lines. A hardware implementation is described that uses only a FIFO register and a display memory. Rapid prototyping using an ARM processor with FPGA resources is achieved to validate the operation of the described system. Experimental results of the implemented design demonstrated the expected operation of the reduced complexity architecture in term of needed memory. Also, the performance of retrieved images were increased.

Logarithmic programmable preamplifier dedicated to ultrasonic receivers

This paper concerns the design, the implementation and the validation of a fully integrated preamplifier dedicated to ultrasonic receivers. The preamplification technique is based on two amplification stages: a logarithmic stage called True Logarithmic Amplifier (TLA) and a programmable-gain module built around a Timing Gain Compensator (TGC). The TLA largely amplifies small amplitude signals, and moderately the large amplitude ones. However, the TGC is used to compensate signal attenuation caused by its traveling several human body tissues. Those main building blocks of an ultrasonic receiver are realized using CMOS 0.35 /spl mu/m technology. Spectre simulations of both the TLA and TGC show unity gain bandwidths of 100 MHz and 127 MHz respectively when driving a load of 1 pF. Measurements of the fabricated chip are done in our laboratory using an external digital controller programmed in FPGA. The total chip area is 7.2 mm/sup 2/ including the digital part needed to program the TGC.

Integrated front-end preamplifier dedicated to ultrasonic receivers

This paper concerns the design and implementation of an integrated front-end preamplifier dedicated to ultrasonic receivers. A new preamplification technique composed of a logarithmic amplifier and followed by a programmable-gain amplifier is proposed. The logarithmic amplifier, based on a True Logarithmic Amplifier (TLA) technique, largely amplifies small amplitude signals, and moderately the large amplitude ones. The programmable-gain amplifier, based on Timing Gain Compensator (TGC), is used to compensate signal attenuation caused by its traveling several human body tissues. Spectre simulations of both the TLA and TGC show unity gain bandwidths of 100 MHz and 127 MHz respectively when driving a load of 1 pF. The implementation of this system (TLA, TGC) is done using CMOS 0.35 /spl mu/m technology. The total chip area is 7.2 mm/sup 2/ including the digital part needed to program the TGC.

Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming

The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18 /spl mu/m technology and the resulting active layout area is 0.14 mm/sup 2/, while its total power consumption is below 40 mW.

A scan conversion CMOS implementation for a portable ultrasonic system

Digital scan conversion is the process of converting received ultrasound signals (echoes) in multiscan lines, at varying angles (polar coordinate), to a Cartesian raster format for displaying. This conversion is necessary for compatibility with LCD and CRT monitors. To avoid artifacts during the conversion process the processed data are interpolated to produce the final memory image. The available interpolation methods typically require the use of two large memories, one for the interpolation and the other for the image display. In this paper, we use a simpler nearest-neighbor interpolation technique combined with the linear interpolation between adjacent scan lines to reduce artifacts on the far field. A hardware architecture is proposed that only uses a FIFO register and a memory for display. CMOSP18 technology is used to implement the described system. The proposed architecture is able to both reduce the complexity of the needed memory and increase the performance of the image processing.

A smart lock system using Wi-Fi security

In large apartment complexes, fraternities, or even for an owner having many keys for each and every apartment, car, or gate he owns, maintaining entry to authorized personnel only is a problem. Besides the costs involved in fabrication, duplication, and distribution of keys, there are security problems in case of lost keys. In this paper an innovative lock system prototype using todays technologies will be presented. The novelty of this prototype relies on the fact that using new technologies along with old ones will result in a smart and more efficient. We propose a smart digital door lock system for any lock system. A digital door lock system is any equipment that uses the digital information such as a secret code instead of the legacy key system. In our proposed system, a Central Control module is embedded in the door itself, this is required to prevent additional complications and more robust mechanism for the door as a whole. Technically, this system embeds itself in the Local Area Network of the house. This adds extra security layers and prevents access to the system only through the network. Furthermore, the biggest advantage of the proposed system over existing ones is that it can be easily installed with minimal requirement of infrastructures and planning.

Perception SoC based on an ultrasonic array of sensors: efficient DSP core implementation and subsequent experimental results

We are concerned with the design, implementation, and validation of a perception SoC based on an ultrasonic array of sensors. The proposed SoC is dedicated to ultrasonic echography applications. A rapid prototyping platform is used to implement and validate the new architecture of the digital signal processing (DSP) core. The proposed DSP core efficiently integrates all of the necessary ultrasonic B-mode processing modules. It includes digital beamforming, quadrature demodulation of RF signals, digital filtering, and envelope detection of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a angle of view span. The design uses a minimum size lookup memory to store the initial scan information. Rapid prototyping using an ARM/FPGA combination is used to validate the operation of the described system. This system offers significant advantages of portability and a rapid time to market.

An Educational Board for Teaching Microcontroller System Design Laboratory

Teaching undergraduate electrical and computer engineering students microcontroller/microprocessor design concepts is essential in today’s highly advanced technological environment. Furthermore, we believe that all engineering students should take an introductory course in this area. With this objective in mind, we have developed an educational board to teach microcontroller circuit design laboratory. The development board is based on PIC16F877A microcontroller from Microchip. In addition, essential software routines, and a laboratory manual that contains a list of design-applications experiments are part of this lab.