Ali Massoud Haidar

A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection

This paper presents a comprehensive modelling methodology for the electromagnetic immunity of integrated circuits (ICs) to direct power injection (DPI). The aim of this study is to predict the susceptibility of ICs by the means of simulations performed on an appropriate electrical model of different integrated logic cores located in the same die. These cores are identical from a functional point of view, but differ by their design strategies. The simulation model includes the whole measurement setup as well as the integrated circuit under test, its environment (PCB, power supply) and the substrate model of each logic core. Simulation results and comparisons with measurement results demonstrate the validity of the suggested model. Moreover, they highlight the interest of the aforementioned protection strategies against electromagnetic disturbances.

LOGO overcome combinational logic limitations

The VLSI/ULSI performance is expected to keep improving at the current rate indefinitely as feature size shrinks; however as chips are bursting with huge number of transistors, the interchip connections are increased and heat dissipation is becoming an enormous problem as more and more functions are gathered on the same chip. This will influence size and performance of chips. LOGO (logic oriented) neural network are presented as a solution. The LOGO neural network is a modeling system aimed to optimize and to improve the parallelism of logical networks; it is able to perform several independent computations in parallel by a single network. LOGO neural networks, powerful tools in both binary and multi-valued logic, are used in this paper to implement multi-valued logic circuits. These networks are designed and optimized using Reed Muller algebra and simplification methods. All these networks are simulated using MATLAB Simulink and showed successful results. These neural networks are proved to overperform ordinary combinational logic networks

Hexadecimal to binary conversion using multi-input floating gate complementary metal oxide semiconductors

Multiple-input floating gate MIFG-MOSFETs and Floating Gate Potential Diagrams FPD used for conversion of quaternary-valued input, octal-valued input and hexadecimal into corresponding binary-valued output in CMOS integrated circuit design environment. The method is demonstrated through the design of a circuit for conversion of octal into the corresponding binary bits (binary 000-111) and for conversion of hexadecimal into the corresponding binary bits (binary 0000-1111) in a standard 1.5μm digital CMOS technology. The conversion method is simple and compatible with the present CMOS process.

A novel neural network half adder

This paper focuses upon the design of neural network to produce good solution to multiple-valued logic circuits. The theoretical basis for applying neural networks to multiple-valued logic algebra called neuro-algebra is proposed. This research also studies the design of a single artificial neural network model for half adders of binary, ternary, quaternary and quinary systems. The model has proven its efficiency with these four different radices. The advantages of the proposed multiple-valued logic algebra, neuro-algebra, are: supervised learning capability, simplicity of the neural network design, high performance, suitability for digital applications, straightforwardness of hardware implementations. The results demonstrate that it is possible to employ a systematic approach in designing neural networks for digital systems and that large-scale neural networks are capable of yielding high-quality solutions to complex problems.

AGC with signal offset and peak-to-peak amplitude stabilization through feedback control

In modern electronic systems, signal stability is a crucial issue. Many methods have been developed to mitigate the deviation from an ideal signal. One of them is called Automatic Gain Control, which tracks variation in an input signal to settle output amplitude. This paper proposes a Differential Automatic Gain Controller with offset stability. It is a Proportional Integral Derivative controller that stabilizes the gain and offset simultaneously. The proposed model is simulated using Pspice, and the simulation shows that accurate results are obtained across frequencies from 1KHZ to 10GHZ. It also indicates that the error tolerance is 0.08% for amplitude and 0.38% for offset in the worst case.

Bio-mimetic approach in digital artificial neuro-science

This paper presents a new field of artificial neuro-science, providing a group of mathematical relations and functional algorithms used to operate and improve Digital Artificial Neural Network models. It introduces all the main properties and characteristics of the digital artificial neurons by providing a modern platform of design and implementation of these intelligent artificial organisms. The modern digital design is initialized by a reservation of memory registers to hold the inputs, outputs and weights. A sequence of binary equivalence comparison operations of the inputs and weights is executed to deliver the required outputs as declared. This novel process provides a mere design and learning road-map to the designer, leading to a massive practice in artificial neural networks.

Identifying the Effective Parameters for Vertical Handover in Cellular Networks Using Data Mining Techniques

The need for seamless mobility within the heterogeneous environment of cellular networks imposed the need for finding different vertical handover (VHO) mechanisms to select the best network. The selection process is based on different factors, such as: cost, battery status of Mobile Terminal (MT), the capacity of each network link, available bandwidth (ABW), received signal strength (RSS), etc. However, the major problem here is to find the most effective parameters for VHO and their priorities for these decision mechanisms. Besides, it would be useful to know the values of these parameters for data mining (DM). For this purpose, we collected real log data server of two mobile telecom companies in Lebanon, Touch and Alfa for Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS) networks. After preprocessing and discretizing the data, frequent patterns (FP) were extracted to summarize the log data files. The summarized data was then analyzed by using descriptive and visualization techniques in order to find the most effective parameters for handover (HO) process. Three effective parameters were obtained: the Received Signal Strength (RxLev/RSCP), the Available Bandwidth (ABW) and the Received Signal Quality (RxQual/EcNo). Results showed that they cooperatively work together to accomplish the same task. This paper provide an effective solution to identify the most valuable factors for vertical handover mechanism in telecommunication area by using frequent pattern mining.

A novel Petri net model for image segmentation Entropic thresholding based methods

This paper presents a Petri net-based hierarchical architecture for image segmentation concept; the work shows our analytical methodologies for modeling and analysis of image segmentation entropic thresholding based methods. The goal of this paper is to model the image segmentation concept using Petri net.

Neuro-SRAM technology

A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.

Octal to binary conversion using multi-input floating gate complementary metal oxide semiconductors

Multiple-input floating gate MIFG-MOSFETs and Floating Gate Potential Diagrams FPD used for conversion of quaternary-valued input and octal-valued input into corresponding binary-valued output in CMOS integrated circuit design environment. The method is demonstrated through the design of a circuit for conversion of quaternary quats into the corresponding binary bits (binary 00–11) and for conversion of octal octets into the corresponding binary bits (binary 000–111) in a standard 1.5μm digital CMOS technology. The novelty of this method is the simplicity of conversion where the output of the convertor can be directly connected to the binary CMOS circuits without the need of any interface due the compatibility of this convertor with the present CMOS process.