Abdel Ejnioui

Control and data flow graph extraction for high-level synthesis

The first step in high level synthesis consists of translating a behavioural specification into its corresponding register transfer language (RTL) description. Behavioural specifications are composed by writing code in a hardware description language such as VHDL. The process of translation starts by first deriving a control and data flow graph (CDFG) from the source code of the behavioural specification. The derivation of the CDFG has been mostly done manually, which makes this process time-consuming and error-prone at least in the earlier stage of synthesis. In this paper, we describe a tool that we have developed for automatic conversion of the given VHDL behavioural specification of a circuit into its corresponding CDFG. Since there is no widely accepted format for representing CDFGs, we opted to make the tool generate several representations of the derived CDFG in different formats to accommodate different implementation approaches. This design decision makes our tool quite flexible and highly useful. The proposed tool has been tested on operation and control-dominated behavioural specifications to ensure its accuracy. Experimental results on benchmark circuits show that the tool is highly accurate and can produce a CDFG in a few seconds using minimal computing resources.

Design and implementation of double precision floating point division and square root on FPGAs

This paper presents the sequential and pipelined designs of a double precision floating point divider and square root unit. The pipelining of these units is based on partial and full unrolling of the iterations in low-radix digit recurrence algorithms. These units are synthesized to produce common-denominator implementations that can be mapped on any FPGA chip regardless of architectural differences between the chips. The implementations of these designs show that their performances are comparable to, and sometimes higher than, the performances of non-iterative designs based on high radix numbers. While the iterative divider and square root unit occupy less than 1% of an XC2V6000 FPGA chip, their pipelined counterparts can produce throughputs that reach the 100 MFLOPS mark by consuming a modest 8% of the chip area. The pipelining of these iterative designs target high throughput computations encountered in some space applications

Design partitioning on single-chip emulation systems

In this paper, we address the problem of partitioning a large design on a reconfigurable single-chip emulator under resource constraints. First, we extract an acyclic flow graph of the design to be emulated. Then, we model the problem as an integer linear programming problem (IP) based on the acyclic flow graph of the design where the structure of the assignment and precedence constraints produce a tight formulation. This formulation is suitable for small designs. For larger designs, we generate a smaller formulation of the integer programming problem based on a reduced form of the acylic graph. Then we use an incremental iterative technique to keep the problem formulation as small as possible. To partition a large design, our algorithm uses two distinct steps with different objectives. In the first step, we minimize the number of cycles needed to schedule every lookup table (LUT) in the circuit. Then flip-flops (FFs) are inserted into the appropriate cycles of the schedule in the second step. Experiments are conducted on small and moderately large circuits from the MCNC Partitioning93 benchmark suite. The obtained results show that our algorithm produces optimal partitioning schedules.

Multiterminal net routing for partial crossbar-based multi-FPGA systems

Multi-FPGA (field-programmable gate arrays) systems are used as custom computing machines to solve compute-intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multiterminal nets in a multi-FPGA system that uses partial crossbars as interconnect structures. First, we model the multiterminal routing problem as a partitioned bin-packing problem and formulate it as an integer linear programming problem where the number of variables is exponential. A fast heuristic is applied to compute an upper bound on the routing solution. Then, a column generation technique is used to solve the linear relaxation of the initial master problem in order to obtain a lower bound on the routing solution. This is followed by an iterative branch-and-price procedure that attempts to find a routing solution somewhere between the two established bounds. In this regard, the proposed algorithm guarantees an exact-routing solution by searching a branch-and-price tree. Due to the tightness of the bounds, the branch-and-price tree is small resulting in shorter execution times. Experimental results are provided for different netlists and board configurations in order to demonstrate the algorithms performance. The obtained results show that the algorithm finds an exact routing solution in a very short time.

Tiered Algorithm for Distributed Process Quiescence and Termination Detection

The Tiered Algorithm is presented for time-efficient and message-efficient detection of process termination. It employs a global invariant of equality between process production and consumption at each level of process nesting to detect termination, regardless of execution interleaving order and network transit time. Correctness is validated for arbitrary process launching hierarchies, including launch-in-transit hazards, where processes are created dynamically based on runtime conditions for remote execution. The performance of the Tiered Algorithm is compared to three existing schemes with comparable capabilities, namely, the Chandrasekaran and Venkatesan (CV), Lai, Tseng, and Dong (LTD), and Credit termination detection algorithms. For synchronization of X tasks terminating in E epochs of idle processing, the tiered algorithm is shown to incur O(E) message count complexity and O(T lg T) message bit complexity while incurring detection latency corresponding to only integer addition and comparison. The synchronization performance in terms of message overhead, detection operations, and storage requirements are evaluated and compared across numerous task creation and termination hierarchies.

Pipelining of double precision floating point division and square root operations

Space applications rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be compiled on DSP processors, high data rate DSP computations require novel implementation technologies to support their high throughputs. Only recently, gate densities in FPGAs have reached a level which makes them attractive platforms to implement compute-intensive DSP applications. In this context, this paper presents the sequential and pipelined designs of a double precision floating point divider and square root unit on FPGAs. Contrary to pipelined parallel implementations, the pipelining of these units is based on unrolling the iterations in low-radix digit recurrence algorithms. These units are mapped on generic FPGA reconfigurable fabric without taking advantage of any advanced architectural components available in high capacity FPGAs. The implementations of these designs show that their performances are comparable to, and sometimes higher than, the performances of non-iterative designs based of high radix numbers. The iterative divider and square root unit occupy less than 1% of an XC2V6000 FPGA chip while their pipelined counterparts can produce throughputs that reach the 100 MFLOPS mark by consuming a modest 8% of the chip area.

A support vector machine for terrain classification in on-demand deployments of wireless sensor networks

Terrain characteristics can significantly alter the quality of the results provided by the deployment methodology of large-scale wireless sensor networks. For example, transmissions between nodes that are heavily obstructed will require additional transmission power to establish connection between nodes. In some cases, heavily obstructed areas may prevent nodes from establishing a connection at all. Therefore, terrain analysis and classification of specific deployment areas should be incorporated in the methodology process for evaluation and optimization of the performance of wireless sensor networks upon deployment. Although there exists radio frequency (RF) models capable of modeling obstructions, such as vegetation, foliage, etc., automatic assignment of parameter values for these models may be troublesome, specifically in highly irregular deployments terrains, where proximity of poor and optimal conditions for signal propagation may be adjacent to each other. In these situations, parameter estimation for modeling terrain obstruction may result in overly optimistic or pessimistic results, causing characterizations or predictions that deviate from the true performance of the WSN once deployed. This paper presents the results of employing a support vector machine for automatic terrain classification. The approach can be used to automatically determine areas of high obstruction, which is essential to estimate obstruction parameters in simulations and enhancing the overall decision-making process during pre-deployment of large-scale and irregular deployment terrains.

Software requirement prioritization using fuzzy multi-attribute decision making

Although many approaches have been proposed to prioritize requirements in software projects, almost none has been widely adopted. This is mostly due to their complexity, time commitment, lack of consistency, or implementation difficulties. This paper proposes a novel approach to do so that is practical, easy to implement and can show a reasonable level of consistency. In addition, it takes in consideration the imprecise nature of requirements and quality attributes by modeling the latter as fuzzy variables. The problem of prioritizing requirements is formulated as a fuzzy multi-attribute decision problem in which the expected value operator is used to rank the alternatives listed in the problem formulation. This approach can be easily extended to include other quality attributes as well as customized to fit the needs of most software projects.

Routing on switch matrix multi-FPGA systems

In this paper, we address the problem of routing nets on multi-FPGA systems interconnected by a switch matrix. Switch matrices were introduced to route signals going from one channel to another inside the FPGA chips. We extend the switch matrix architecture proposed by Zhu et al. (1993) to route nets between FPGA chips in a multi-FPGA system. Given a limited number of routing resources in the form of programmable connection points within the two-dimensional switch matrix, this problem examines the issue of how to route a given net traffic through the switch matrix structure. First we formulate the problem as a general undirected graph in which each vertex has one single color. Since there can be at most six colors in the entire graph, the problem is defined as a search for at most six independent vertex sets of each color in the graph. We propose an exact solution for this problem that is suitable only for small size switch matrices. For large size switch matrices used in multi-FPGA systems, we convert the graph-theoretic formulation to a constraint satisfaction problem. Due to its large size, we then model the constraint satisfaction problem as a 0-1 multi-dimensional knapsack problem for which a fast approximate solution is applied. Experiments were conducted on switch matrixes of various sizes to measure the performance of the proposed approximate solution. The results show that the performance of our proposed heuristic improves with the increasing size of the switch matrixes.

Prioritisation of software requirements using grey relational analysis

While many efforts have been undertaken to prioritise requirements in software projects, almost none has shown practical methods to do so. Most methods that produce consistent results tend to be complex and consequently difficult to implement. On the other hand, informal methods can save time and are easy to implement, but lack the structure and consistency needed to reliably analyse requirements. This paper introduces a new approach for prioritising software requirements. Because of the imprecise nature of requirement and attribute data, this approach represents the problem as a grey multi-attribute decision problem by relying on grey relational analysis to address this decision problem. In addition, the approach allows decision makers to use an objective or subjective weighting scheme to model the importance of attributes before solving the decision problem. This approach is practical and can be easily implemented as a decision making tool to assist decision makers in prioritising requirements.