Nagarajan Ranganathan

High-performance flow-focusing geometry for spontaneous generation of monodispersed droplets

A high-performance flow-focusing geometry for spontaneous generation of monodispersed droplets is demonstrated. In this geometry, a two-phase flow is forced through a circular orifice integrated inside a silicon-based microchannel. The orifice with its cusp-like edge exerts a ring of maximized stress around the flow and ensures controlled breakup of droplets for a wide range of flow rates, forming highly periodic and reproducible dispersions. The droplet generation can be remarkably rapid, exceeding 10(4) s(-1) for water-in-oil droplets and reaching 10(3) s(-1) for oil-in-water droplets, being largely controlled by flow rate of the continuous phase. The droplet diameter and generation frequency are compared against a quasi-equilibrium model based on the critical Capillary number. The droplets are obtained despite the low Capillary number, below the critical value identified by the ratio of viscosities between the two phases and simple shear-flow.

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

Because of Moores (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21×21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 µm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25×25×0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45×45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Buried microfluidic channel for integrated patch-clamping assay

The authors present a microfluidic device towards an integrated patch-clamping assay. The device replaces conventional glass patch pipette with a buried microfluidic channel on silicon substrate. The microchannel fabrication involves reforming doped glass under heat and pressure, a process, in principle, analogous to the heat-pulling/polishing of glass patch pipettes. Unlike etching substrate, this process leaves a smooth glass surface for seal formation with cell membrane. The microchannel is evolved from a trapped void inside the trench during nonconformal deposition of the doped glass. The results of seal formation with mammalian cells captured at such microchannel opening are presented.

Integration of high aspect ratio tapered silicon via for through-silicon interconnection

This paper provides a detailed overview of silicon carrier based packaging for 3D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a 3-step approach has been developed and characterized which controls via depth, sidewall profile and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.

FCBGA Package With Through Silicon via (TSV) Interposer

A two-axis in-plane capacitive accelerometer fabricated on silicon-on-insulator (SOI) is developed. With each stationary electrode separated to two sub stationary electrodes by refilled isolation trench, the presented accelerometer has compact differential capacitance electrodes to improve capacitance sensitivity per sensing area. In addition, the overlap area-changed capacitor enables good linearity and low damping coefficient.

Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication

This note describes a new high-throughput process of polyimide etching for the fabrication of MEMS devices with an organic sacrificial layer approach. Using dual frequency superimposed capacitively coupled plasma we achieved a vertical profile of polyimide with an etching rate as high as 3.5 µm min−1. After the fabrication of vertical structures in a polyimide material, additional steps were performed to fabricate structural elements of MEMS by deposition of a SiO2 layer and performing release etching of polyimide.

Compact electrode design for an in-plane accelerometer on SOI with refilled isolation trench

The building blocks of the 3-D IC integration technology are Through-Silicon Via (TSV) fabrication/implementation, thin wafer handling, low-temperature backside TSV revealing process, and electrical redistribution or connection of vertical circuitry or ICs. Of these elements, the scheme for wafer thinning and backside passivation is a crucial technology element of 3D integration. In this paper, novel backside via revealing and passivation for 3D IC application is proposed with newly developed process integration. Si/Cu CMP process is applied to overcome the practical limitations on the uniformity of the backside thinning originated from the blind thinning process. As such, the height variations associated with via etch non-uniformity and glue, carrier and grinding TTVs (Total Thickness Variation) are flattened out. In order to protrude the TSV from the backside, we demonstrated new spin wet etchback process with well-controlled repeatability, reduced process defect and copper contamination. For the low-k thick dielectric layer application (without photo-litho), Insulation layer on the back side is deposited over the protruded portion of the TSV structure. The deposited insulation layer is removed and TSV area is again exposed. The process for removing this insulation layer is the plasma etching or CMP polish.