Abderrahim Doumar

Defect and fault tolerance FPGAs by shifting the configuration data

The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGAs configurable logic blocks (CLBs). The defects affecting the FPGAs interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and horse-allocation) are introduced and compared.

Testing the logic cells and interconnect resources for FPGAs

This paper presents a new design for testing SRAM based field programmable gate arrays (FPGAs). The new proposed method is able to test both the configurable logic blocks (CLBs) and the interconnection networks. The proposed design is based on slightly modifying the original SRAM part in the FPGA so that it will allow the configuration data to be looped on a chip and then the test becomes easier. This method requires a very short test time compared to the previous works. Moreover, the off-chip memory used in the storage of the configurations data is considerably reduced. The application of this method to the XC4000 family and ORCA shows that (relative to that required by the previous works) the test time can be reduced by 87.2% and the required off-chip memory can be reduced by 88.6%.

Design of an automatic testing for FPGAs

This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original SRAM part is modified a bit so that the FPGA gets the ability to automatically shift the data on-chip and then the test becomes faster. This method does not need a large outside memory (off-chip memory) for saving the test data. It is proved that this method detects multiple faults and covers 100%; of modeled faults. The simulation results of Xilinix XC4000 family, using CAD tools, shows that the routing and the placement of this method are easily achieved.

Design of switching blocks tolerating defects/faults in FPGA interconnection resources

Field programmable gate array is mainly composed of the interconnection resources area. Related defects/faults are therefore more probable than defects/faults in other regions of the chip. In this paper we propose a new approach tolerating defects/faults in interconnection resources. This approach is based on the modification of the switching block structure so that defects/faults could be avoided. Defects/faults are avoided with only an average of 3% delay overhead and partial modification of the original data. The yield is significantly improved comparing with actual chips. The area overhead is required in this approach. However, it is proved that it is reasonable comparing with other approaches.

Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift

In this paper, a new design for online testing of system on a chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which keeps its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances.

Testing approach within FPGA-based fault tolerant systems

Proposes a test strategy for FPGAs to be applied within FPGA-based fault-tolerant systems. We propose to make some configurable logic blocks (CLBs) under test and to implement the rest of the CLBs with the normal user data. In the target fault-tolerant systems, there are two phases (the functional phase and the test phase). In the functional phase, the system achieves its normal functionality, while in the test phase, the FPGA is tested. In this phase, the configuration data of the CLBs under test are shifted on-chip in parallel to other CLBs for achieving the test in these CLBs. All the CLBs are tested in a single test phase. The shifting process control, test application and test observation are achieved by the logic managing the fault tolerance (from outside the chip). The system returns to its normal phase after all the CLBs have been scanned by the test. The application of this approach reduces the fault tolerance cost (hardware, software, time, etc). The user is then able to periodically test the chip using only the data inside the chip and without destroying the original configuration data. No particular hardware is required for saving the test data on-board. Additionally, no particular software treatment is required for the test. The testing time is reduced enormously. Unfortunately, as a consequence of implementing two types of data on-chip, a 15% decrease in the chip functionality and a 2.5% delay overhead are noticed in the case of structures similar to a 20/spl times/20 Xilinx FPGA.

An automatic testing and diagnosis for FPGAs

This paper presents a new design for testing and diagnosing the SRAM-based field programmable gate arrays (FPGA). By slightly modifying the original FPGAs SRAM memory, the new architecture permits the configuration data to be looped on a chip. Then the full testing and diagnosing of the FPGA are achieved by loading typically only one testing configuration datum (carefully chosen) instead of loading the total required configurations data (which is a very slow process) in the normal cases. Other configurations data are obtained by shifting the first one inside the chip. Consequently the test becomes faster. This method does not need a large outside memory (off-chip memory) for the test. The evaluation proves that this method becomes very interesting when the complexity of the configurable blocks (CLBs) or the chip size increase.