Kentaroh Katoh

A Delay Measurement Technique Using Signature Registers

This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18μm process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit

This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54%. It is 6.62% smaller than the conventional method, and 8.41% larger than standard scan design.

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The pro- posed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-μm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

Analog/mixed-signal circuit design in nano CMOS era

This paper describes analog/mixed-signal circuit design in the nano CMOS era. Digitally-assisted analog technology is becoming more important, and as an example, our fully digital FPGA implementation of a TDC with self-calibration is shown. Since pure analog circuits are still present and “good” device modeling is required for their designs, device modeling technology for nano CMOS with complicated behavior is also reviewed.

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices

This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-I, a coarse grained dynamically reconfiguration processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead

Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift

In this paper, a new design for online testing of system on a chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which keeps its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances.

Experimental verification of timing measurement circuit with self-calibration

This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable System-on-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators

This paper presents a theoretical analysis of the stochastic calibration of TDC using two ring oscillators. Designers of TDC with the calibration function have to decide the design parameters to guarantee the convergence of error and valid calibration time. The basic theory of the calibration is useful to decide these parameters and the policy on the calibration design. The performance of the stochastic calibration depends on the design parameters, the frequencies of the two ring oscillators, the number of the stages, the buffer delay, and so on. This work analyzes explicitly the relation between these parameters and the performance of the calibration with simulation-based analysis. Simulation results reveal that the convergence of the calibration is guaranteed when both of the cycles of the two ring oscillators are the prime cycles. The histogram of each bin converges to the corresponding buffer delay value in a well-behaved manner, the DNL measurement error decreases monotonically in proportion to the increase of the number of the times of the measurement. In other words, the required number of the measurement times is in proportion to the required accuracy of calibration. This result is applied to the calibration of VDL-based TDC, too.

Time-to-digital converter architecture with residue arithmetic and its FPGA implementation

This paper describes a time-to-digital converter (TDC) architecuture with residue arithmetic or Chinese Remainder theorem. It can reduce the hardware and power significantly compared to a flash type TDC while keeping comparable performance. Its FPGA implementation and measurement resuts show the effectiveness of our proposed architecture.

A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator

This paper proposes a small chip area stochastic calibration for TDC linearity and input range, and analyzes it with FPGA. The proposed calibration estimates the absolute values of the delay of the buffers and the range of measurement statistically. The hardware implementation of the proposed calibration requires single counter to construct the histogram, so that the extra area for the proposed calibration is smaller. Because the implementation is fully digital, it is easily implemented on digital LSIs such as FPGA, micro-processor, and SoC. Experiments with Xilinx Virtex-5 LX FPGA ML501 reveal that both the periods of the external clock and the ring oscillator are preferred as short as possible under more than twice of the range of measurement of TDC when the oscillation period of the ring oscillator is wider than that of the external clock for fast convergence. The required time for the proposed calibration is 0.08 ms, and the required hardware resources LUTs and FFs for the implementation on FPGA are 24.1% and 22.2% of the conventional implementation, respectively.