Abdessalem Ben Abdelali

Combining Haar Wavelet and Karhunen Loeve Transforms for Medical Images Watermarking

This paper presents a novel watermarking method, applied to the medical imaging domain, used to embed the patients data into the corresponding image or set of images used for the diagnosis. The main objective behind the proposed technique is to perform the watermarking of the medical images in such a way that the three main attributes of the hidden information (i.e., imperceptibility, robustness, and integration rate) can be jointly ameliorated as much as possible. These attributes determine the effectiveness of the watermark, resistance to external attacks, and increase the integration rate. In order to improve the robustness, a combination of the characteristics of Discrete Wavelet and Karhunen Loeve Transforms is proposed. The Karhunen Loeve Transform is applied on the subblocks (sized 8 × 8) of the different wavelet coefficients (in the HL2, LH2, and HH2 subbands). In this manner, the watermark will be adapted according to the energy values of each of the Karhunen Loeve components, with the aim of ensuring a better watermark extraction under various types of attacks. For the correct identification of inserted data, the use of an Errors Correcting Code (ECC) mechanism is required for the check and, if possible, the correction of errors introduced into the inserted data. Concerning the enhancement of the imperceptibility factor, the main goal is to determine the optimal value of the visibility factor, which depends on several parameters of the DWT and the KLT transforms. As a first step, a Fuzzy Inference System (FIS) has been set up and then applied to determine an initial visibility factor value. Several features extracted from the Cooccurrence matrix are used as an input to the FIS and used to determine an initial visibility factor for each block; these values are subsequently reweighted in function of the eigenvalues extracted from each subblock. Regarding the integration rate, the previous works insert one bit per coefficient. In our proposal, the integration of the data to be hidden is 3 bits per coefficient so that we increase the integration rate by a factor of magnitude 3.

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Adaptive systems based on FPGA architectures can benefit greatly from the high degree of flexibility offered by Dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. The limitations in the existing tools provided by major FPGA manufacturers do not allow an efficient placement and relocation of variable-sized hardware tasks. This paper presents a design method for relocation of variable-sized hardware task on SRAM-based FPGAs for adaptive systems using dynamic partial reconfiguration (DPR). The proposed relocation procedure takes into account the communication between different reconfigurable regions and static region. This work gives a detailed description of the proposed partial bitsream relocation of variable-sized hardware tasks targeting the Virtex-5 FPGAs.

Efficient BinDCT hardware architecture exploration and implementation on FPGA.

Graphical abstract

Design and implementation of an RGB to HMMD color conversion module on FPGA

In this paper, we propose a hardware architecture to implement a RGB to HMMD Color space converter. This converter presents a fundamental module for the color structure descriptor (CSD) extraction. The CSD provides a high satisfactory image indexing and retrieval results among all MPEG-7color-based descriptors, but the real time implementation of this descriptor still having problems. We propose a hardware implementation of the RGB to HMMD block using Field Programmable Gate Arrays (FPGAs). The proposed implementation architecture can efficiently operate under real time video processing constraints. We have used a new FPGA family to implement the proposed architecture. Synthesis and simulation results of the developed hardware module are given to demonstrate the effectiveness of the implemented architecture and to show the simulations results for a real input image.

Adequation and hardware implementation of the color structure descriptor for real-time temporal video segmentation

AbstractIn this paper, we focused on the study of the MPEG-7 color structure descriptor (CSD) for real-time temporal video segmentation. A new hardware architecture of the CSD was proposed. In the aim of optimizing this implementation in terms of hardware resources and execution time, different algorithm transformations have been tested for the considered application. The CSD was applied for different quantization levels in the HMMD color space and for different grey levels, with and without a frame skip. We have demonstrated that the use of a low number of quantization levels and a frame skip can significantly reduce the complexity and assure a better computing performance while preserving a satisfactory level of accuracy in terms of shot boundary detection rate. This is useful for implementation on resource-constrained hardware platform and multiprocessing applications. The performances of the proposed architecture were evaluated for different quantization levels to show the effect on occupied hardware resources and execution time. The comparative study demonstrates the effectiveness of the proposed architecture, which can operate in real-time video and without restriction on image size. In this work we have also designed a system on chip (SOC) for real-time video summarization based on the CSD. The proposed SOC integrating the CSD module was developed using a platform based on a Xilinx Virtex5 FPGA. A complete demonstration, including CSD extraction, shot boundary detection and key-frames visualization, was realized.

FPGA-based SOC for hardware implementation of a local histogram-based video shot detector

In this paper, we present a video application example and its implementation in a reconfigurable system-onchip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse hardware module versions corresponding to different quantization levels and architectural solutions for an LH-based shot detection system are presented. The developed modules have different hardware resource occupations and can be used in a dynamic way to allow flexible management of the target hardware system. They also show high execution time efficiency and can reach an important bandwidth that can support the most recent high-resolution video formats with a high rate of frames per second. A complete SOC-based demonstration for video summarization based on the LH is also developed. It includes the LH extraction, shot boundary detection, and key frame visualization.

High-level design flow and environment for FPGA-based dynamic partial reconfiguration

ABSTRACT The main motivation of this paper is related to the lack of a high-level design flow for field-programmable gate array (FPGA) partial dynamic reconfiguration management. Our contribution consists in proposing a high-level add-on methodology to the Xilinx’s design flow for dynamic partial reconfiguration (DPR). The main objective is to give an abstract view of the developed application in order to facilitate the designer task. The suggested design flow offers an application-centric view on dynamic reconfiguration designs, which permits simplifying the optimisation and generation of such designs. A new formulation of the reconfigurable modules’ mapping process is put forward. This allows a design space exploration so as to find the convenient number of reconfigurable regions and their sizes as well as the reconfiguration sequence. A new tool was proposed to support our methodology by allowing creating and synthesising graphical models of the developed application. We introduce a new block diagram to represent this latter and a sequence model that can be used for the design optimisations. To validate the proposed DPR design environment, two application examples are given at the end of the paper. They demonstrate the usefulness of the suggested models and methods.

Dynamic reconfigurable architecture for adaptive DCT implementation

In this paper, we propose a reconfigurable architecture for discrete cosine transform (DCT) computation. The objective of the paper is to integrate the DCT computation in a complete embedded system based on ARM processors. Based on dynamic partial reconfigurable FPGAs, different versions of DCT computation are used to give adaptability and flexibility to the architecture. These adaptability responses to different service requirements at run time, such as image quality levels, and system performance. We also explore an efficient management of the reconfigurable area by adjusting the size of the reconfigurable region to the different variable sized hardware module related to the adaptable DCT IP core. The ZedBoard development kit based on the Xilinx Zynq-7000 was used in the study. The results of implementation offer a number of benefits such as optimized hardware resources utilization, efficiently handled the reconfigurable area and reduced reconfiguration time.

Multi-video processing applications on FPGA

With the increasing needs of processing power in video and image processing for advanced media and communication applications, it is mandatory to go further than the software implementation to provide generic, real time, low cost and high performance hardware platforms. In this paper, we present a re-configurable, hardware platform for video and image processing. The proposed system uses the benefits of field programmable gate array FPGA to attain this objective. In this context, a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processor, embedded memory, multi-port memory controller MPMC, standard interfaces, and different other resources. Our system includes different functional modules: video cut detection, video zoom-in and zoom-out. This provides the flexibility of using this system as a general video processing platform according to different application requirements. The final system utilises ∼16% of logic resource and 20% of on chip memory.

Modeling and simulation of 2D-BinDCT based lifting scheme and its integration in a dynamically reconfigurable SOC

The Discrete Cosine Transform (DCT) is the most widely used transform for image compression. The DCT approximation or the Binary Discrete Transform (BinDCT) [1] has shown to be a promising alternative to the DCT for its implementation simplicity, close performance and compatibility to the DCT. In this paper, we aim to present efficient VLSI architectures with a low BinDCT complexity implementation. We explore the design of a hardware BinDCT accelerator, the simulation and implementation of the different proposed architectures for a virtex6 FPGA device and its integration in a dynamically reconfigurable SOC. An IP interface was adopted to be able to integrate the proposed hardware accelerator in a SOC. The dynamic partial reconfiguration technique was applied to toggle between the original DCT and BinDCT versions depending on the application requirement. Complete hardware cores, which can be integrated directly in a SOC, was elaborated in order to accelerate the DCT or the BinDCT transform calculation.