Abdellatif Mtibaa

An efficient list scheduling algorithm for time placement problem

The partially reconfigurable FPGAs allows an overlap between the execution and the reconfiguration of tasks. The partial approach can be used to fit a large application into the FPGA device by partitioning the application over time. The executions being partitioned over time and the configurations of tasks are done so that the imposed constraints are satisfied. The main aim of this work consists in answering the question when will a task be mapped in the FPGA? A time placement algorithm based on the list scheduling technique is developed to solve efficiently the above question. We have just used the list scheduling algorithm because of its fast run time. Compared to the run time of other algorithms used in this filed like the spectral and ILP algorithms, the list scheduling algorithm remains a good temporal placement candidate, especially, for a several nodes graph. Also, a part of this paper is devoted for the study and the implementation of DCT task graph. This graph is the most computationally intensive part of the Color Layout Descriptor algorithm of a low-level visual descriptor of MPEG 7. The studied case shows that the use of the partial approach is very efficient in terms of latency of the whole application than the full one.

Synthesis and Time Partitioning for Reconfigurable Systems

This paper aims to introduce a time partitioning algorithm which is an important step during the design process for fully reconfigurable systems. This algorithm is used to solve the time partitioning problem. It divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal. Also a part of this paper is consecrated for implementation of some examples on a fully reconfigurable architecture following our approach.

A real-time shot cut detector: Hardware implementation

With the enormous growth in digital audiovisual (AV) information in our life, there is an important need for tools which enable describing the AV content information. In this context, the MPEG-7 standard was developed in order to provide a set of standardized description tools which generate metadata about AV content. However, before any content-based manipulations, the hierarchical structure of video must be determined. This process is known as shot boundary detection or in other case scene change detection. In this paper, an old and reliable method based on local histogram has been used to implement shot cut detector for real-time applications. Since software implementation on PC is not suitable for this algorithm due to the sequential treatments of the processor, we have used an FPGA-based platform.

Temporal partitioning of data flow graph for dynamically reconfigurable architecture

Abstract In this paper, we present a novel temporal partitioning algorithm that temporally partitions a data flow graph on reconfigurable system. Our algorithm can be used to resolve the temporal partitioning problem at the behaviour level. Our algorithm optimizes the whole latency of the design; this aim can be reached by minimizing the latency of the graph and the number of partitions at the same time. Consequently, our algorithm starts by the lowest possible number of partitions; and next it uses the eigenvectors of the graph to find the best schedule of nodes that minimizes the latency of the graph. The proposed methodology was tested on several examples on reconfigurable architecture based on Xilinx Vertex-II XC2V1000 FPGA device. The results show significant reduction in the design latency compared to famous related algorithms used in this field.

Partitioning and scheduling technique for run time reconfigured systems

With tremendous improvement in FPGA technologies over the last decade, various high performances, low cost FPGAs are now available. This has enabled the development of cost effective, high speed reconfigurable boards called run time reconfigured (RTR) system. These boards, due to the abundant hardware resource available, enhance the amount of design parallelism by several magnitudes in comparison to ASIC designs of comparable cost. The advent of such high performance FPGA boards has brought a new research problem: the temporal partitioning problem. In the literature, the main objective of related algorithms in this field is to find the minimal execution time of the input graph on a fixed-size of area. However, this paper focuses on introducing a new temporal partitioning algorithm. It divides the input task graph into an optimal number of partitions and puts each task in the appropriate partition in order to decrease the transfer of data required between partitions of the design.

Combining temporal partitioning and temporal placement techniques for communication cost improvement

In this paper, we present a typical temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable system. Our approach optimizes the communication cost of the design. This aim can be reached by minimizing the transfer of data required between design partitions and the routing cost between FPGA modules. Consequently, our algorithm is composed by two main steps. The first step aims to find a temporal partitioning of the graph. This step gives the optimal solution in term of communication cost. Next, our approach builds the best architecture, on a partially reconfigurable FPGA, that gives the lowest routing cost between modules. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field.

Robust road lanes and traffic signs recognition for driver assistance system

Increasing safety and reducing road accidents, thereby saving lives, are one of the great interests in the context of advanced driver assistance systems. Apparently, among the complex and challenging tasks of future intelligent vehicles is road lanes detection and road signs recognition. In this paper, a multitask driver assistance system has been proposed. First, the system provides the driver with real-time information from lanes markers and road signs, which consist of the most important and challenging tasks. Secondly, it generates an acoustic warning to the driver in advance of any danger. This warning then allows the driver to take appropriate corrective actions in order to mitigate or completely avoid the event. The proposed system was tested on real road scene captured from moving vehicle. From the experimental results, the system has demonstrated a robust performance for detecting the road lanes and signs under different conditions.

Implementation on the FPGA of DTC-SVM Based Proportional Integral and Sliding Mode Controllers of an Induction Motor: A Comparative Study

The conventional direct torque control (DTC), based on the hysteresis controllers and the switching table, operates with a variable switching frequency, which decreases the conventional DTC performances, like the torque and flux ripples. Thus, the space vector modulation (SVM), used in the DTC, ensures a constant switching frequency and improves the DTC performances. The first aim of this paper is to present a comparison study between the DTC with an SVM (DTC-SVM) based on the Proportional Integral regulators (DTC-SVM-PI) and the DTC-SVM based on the sliding mode controllers (DTC-SVM-SMC). These two approaches are complex control algorithms which require faster micro-controllers; therefore the second objective of this paper is to present the implementation of the DTC-SVM-PI and the DTC-SVM-SMC on the Field Programmable Gate Array (FPGA), due to the parallel processing capability of the FPGAs. The two approaches are designed and simulated using the Xilinx System Generator (XSG) and implemented using an FPGA Virtex 5. The simulation results in the transient behavior and the steady state of the induction motor controlled by these two approaches are compared and discussed. The hardware FPGA implementation results show the effectiveness of the FPGA relative to the digital signal processor in terms of execution time.

Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement

Purpose – The purpose of this paper is to reduce the reconfiguration time of a field‐programmable gate array (FPGA).Design/methodology/approach – The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time.Findings – Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms.Originality/value – The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well‐known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.

Exploring the temporal placement for partially reconfigurable device

In this paper, we examine the temporal placement, showing how it can be decomposed into a number of distinct but not independent subtasks. Then, we detail the early algorithms that have been developed for solving the temporal placement problem. Next we introduced a new temporal placement algorithm that aims to reduce the routing cast between modules. And finally, experiments are conducted in order to evaluate the complexity and design performances of the proposed algorithm versus others temporal placement algorithms.