Abdsamad Benkrid

A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

This paper presents the design and implementation of the most parameterisable field-programmable gate array (FPGA)-based skeleton for pairwise biological sequence alignment reported in the literature. The skeleton is parameterised in terms of the sequence symbol type, i.e., DNA, RNA, or protein sequences, the sequence lengths, the match score, i.e., the score attributed to a symbol match, mismatch or gap, and the matching task, i.e., the algorithm used to match sequences, which includes global alignment, local alignment, and overlapped matching. Instances of the skeleton implement the Smith-Waterman and the Needleman-Wunsch algorithms. The skeleton has the advantage of being captured in the Handel-C language, which makes it FPGA platform-independent. Hence, the same code could be ported across a variety of FPGA families. It implements the sequence alignment algorithm in hand using a pipeline of basic processing elements, which are tailored to the algorithm parameters. This paper presents a number of optimizations built into the skeleton and applied at compile-time depending on the user-supplied parameters. These result in high performance FPGA implementations tailored to the algorithm in hand. For instance, actual hardware implementations of the Smith-Waterman algorithm for Protein sequence alignment achieve speedups of two orders of magnitude compared to equivalent standard desktop software implementations.

High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons

In this paper, we present a new approach to developing a general framework for efficient FPGA based Image Processing algorithms. This approach is based on the new concept of Hardware Skeletons. A hardware skeleton is a parameterised description of a task-specific architecture, to which the user can supply parameters such as values, functions or even other skeletons. A skeleton contains built-in rules that will apply optimisations specific to the target hardware at the implementation phase. The framework contains a library of reusable skeletons for a range of common Image Processing operations. The library also contains high level skeletons for common combinations of basic image operations. Given a complete algorithm description in terms of skeletons, an efficient hardware configuration is generated automatically. We have developed a library of hardware skeletons for common image processing tasks, with optimised implementations specifically for Xilinx XC4000 FPGAs. This paper presents and illustrates our hardware skeleton approach in the context of some common image processing tasks, based on an implementation on VISICOM’s VigraVision™ FPGA based video board.

Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension

This paper presents four novel area-efficient field-programmable gate-array (FPGA) bit-parallel architectures of finite impulse response (FIR) filters that smartly support the technique of symmetric signal extension while processing finite length signals at their boundaries. The key to this is a clever use of variable-depth shift registers which are efficiently implemented in Xilinx FPGAs in the form of shift register logic (SRL) components. Comparisons with the conventional architecture of FIR filter with symmetric boundary processing show considerable area saving especially with long-tap filters. For instance, our architecture implementation of the 8-tap low Daubechies-8 FIR filter achieves ~ 30% reduction in the area requirement (in terms of slices) compared to the conventional architecture while maintaining the same throughput. Two of the above-cited novel architectures are dedicated to the special case of symmetric FIR filters. The first architecture is highly area-efficient but requires a clock frequency doubler. While this reduces the overall processing speed (to a maximum of 2), it does maintain a high throughput. Moreover, this speed penalty is cancelled in bi-phase filters which are widely used in multirate architectures (e.g., wavelets). Our second symmetric FIR filter architecture saves less logic than the first architecture (e.g., 10% with the 9-tap low Biorthogonal 9&7 symmetric filter instead of 37% with the first architecture) but overcomes its speed penalty as it matches the throughput of the conventional architecture.

Towards a general framework for FPGA based image processing using hardware skeletons

In this paper, we present our approach to developing a general framework for FPGA based Image Processing. This framework is based on a library of hardware skeletons. A hardware skeleton is a parameterised description of a task-specific architecture. A skeletons implementation will apply optimisations specific to the target hardware. The library normally contains a range of alternative skeletons for the same task, perhaps tailored for different data representations. The library also contains high level skeletons for compound operations, whose implementation can apply appropriate optimisations. Given a complete algorithm description in terms of skeletons, an efficient hardware configuration is generated automatically. We have developed a library of hardware skeletons for common image processing tasks, with optimised implementations specifically for Xilinx XC4000 FPGAs. This paper presents and illustrates our hardware skeleton approach in the context of some common image processing tasks. It demonstrates our approach to the broader problem of achieving optimised hardware configurations while retaining the convenience and rapid development cycle of an application-oriented, high level programming model.

Design and implementation of a generic 2D orthogonal discrete wavelet transform on FPGA

This paper presents an FPGA architecture for the separable 2-D Biorthogonal Discrete Wavelet Transform (DWT) decomposition. The architecture is based on the Pyramid Algorithm Analysis, which handles computation along the border efficiently by using the method of symmetric extension. For a J stage wavelet transform of NxN images, our architecture has a period of N² cycles per NxN image, and requires only the minimum intermediate storage size necessary. The architecture is highly scalable for different filter lengths and different octave levels. The design of a specific 2-D Biorthogonal 9&7 Wavelet Transform and its implementation on the Xilinx Virtex-E is taken as a case study.

An FPGA-Based Image Connected Component Labeller

This paper describes an FPGA implementation of a Connected Component Labelling algorithm (CCL), developed at Queen’s University Belfast. The algorithm iteratively scans the input image, performing a non-zero maximum neighbourhood operation. It has been coded in Handel C language and targeted Celoxica RC1000-PP PCI board. The whole design was fully implemented and tested on real hardware in less than 24 man-hour. It uses a Virtex-E FPGA and two banks of off-chip memory. For 1024x1024 input images, the whole circuit consumes 583 FPGA slices and 5 Block RAMs and can run at 72 MHz, leading to a 68 pass/sec performance. The FPGA implementation outperforms, easily, an equivalent software implementation running on a 1.6 GHz Pentium-IV PC. A 10-fold speed up has been realised in many instances.

Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA

This paper presents an FPGA architecture for the separable 2-D Biorthogonal Discrete Wavelet Transform (DWT) decomposition. The architecture is based on the Pyramid Algorithm Analysis, which handles computation along the border efficiently by using the method of symmetric extension. For a J stage wavelet transform of NxN images, our architecture has a period of N² cycles per NxN image, and requires only the minimum intermediate storage size necessary. The architecture is highly scalable for different filter lengths and different octave levels. The design of a specific 2-D Biorthogonal 9&7 Wavelet Transform and its implementation on the Xilinx Virtex-E is taken as a case study.

High level programming for real time FPGA based video processing

The inherent reprogrammability of field programmable gate arrays (FPGAs) gives them some of the flexibility of software while keeping the performance advantages of an application specific hardware solution. However, the main disadvantage of FPGAs is the low level of their programming model. Although software tools have been drastically improved since the early days of this new technology, they still require the user to think at the hardware level rather than at the algorithmic level. To bridge the gap between the application and implementation levels, we present a high level software environment for FPGA based real time video processing, which aims to hide hardware details completely from the user. Our approach is to provide a flexible FPGA-based image processing coprocessor with a very high level programming interface based on the core operators of image algebra. Our system has been successfully implemented on VISICOMs VigraVision/sup TM/ PCI board giving real time processing of video data.

An environment for generating FPGA architectures for image algebra-based algorithms

FPGA technology offers the potential for low cost, high performance for certain applications, including image processing. However, the programming model which FPGAs typically present to application developers is prohibitively low level. This paper presents a software environment and architecture description approach which enable the dynamic generation of FPGA architectures for high level image processing operations based on image algebra. Scaleable, parameterised architectures can be described using a small set of Prolog constructors which specify an architecture as a parameterised composition of base level building blocks. The environment includes a rule-based generator which produces EDIF netlist files for each high level operation, targeted to Xilinx XC6200 series FPGAs.

High Performance Biosequence Database Scanning using FPGAs

This paper presents the design and implementation of a generic and highly parameterised FPGA-based core for pairwise biological sequence alignment. The core is captured in the Handel-C language, which allows for high level software-like descriptions of hardware architectures. It implements the sequence alignment algorithm in hand using a pipeline of basic processing elements. This results in high performance FPGA implementations tailored to the algorithm in hand. For instance, actual hardware implementations of the Smith-Waterman algorithm for protein sequence alignment achieve speed-ups in excess of 100:1 compared to equivalent standard PC-based software implementations.