Abdul Karimi Halim

Logical Effort using a Novel Discrete Particle Swarm Optimization algorithm

Designers often need to choose the gate sizes for logic circuit designs to estimate the delay of the circuit. Simulation and timing analysis are poor tools for this task because they cannot be modified for better results. Hence, the method of Logical Effort (LE) provides a simple method to overcome these design problems. We apply a novel Discrete Particle Swarm Optimization algorithm (DPSO) to solve the LE problem for electronic circuits. The method uses the rescaling function commonly used to scale datasets in neural networks to convert continuous-valued PSO values into discrete values. The proposed algorithm was successfully applied on a three-stage NAND gate circuit, and has been shown to work well, with 100% accuracy in all test runs.

Development of Novel Data Compression Technique for Accelerate DNA Sequence Alignment Based on SmithWaterman Algorithm

This paper presents the development of high performance accelerating technique for DNA sequences alignment. The scope of the paper focuses on speed optimization and memory reduction of the existing technique on initialization module. The novel development of the optimization using data compression technique for accelerates the Smith-Waterman (SW) algorithm has been revealed through this paper. This technique has been implemented on hardware based acceleration device. The development is targeted to Altera Cyclone II 2C70 FPGA and using 50MHz oscillator. The code is written in verilog HDL syntax using Quartus 2 version 7.2 and the simulation is verified using Quartus 2 version 7.2 simulator tool. The theoretical analysis and simulation result based on implementation of the design using FPGA are presented and well organized in this paper. The comparative study based on theoretical and simulation results of this technique has been made to accomplish result of analysis. The compilation result for data compression technique development of SW algorithm consisting of 73 logic elements with 93.75% reduction in memory space requirement.

Development of DNA sequencing accelerator based on Smith Waterman algorithm with heuristic divide and conquer technique for FPGA implementation

In this paper, a new approach is introduced to reduce the complexity of the Smith Waterman algorithm for FPGA implementation. We have developed the technique for the fastest comparison of the two DNA sequencing using Verilog on the Xilinx ISE 7.1. The Simulation has been running on the ModelSim XE III 6.0. The combinational delay for the proposed smith waterman algorithm based on divide and conquers technique sequencing is 10.214 ns while the original is 10.295 ns. We have proved that smith waterman algorithm based on divide and conquers technique gives better performance than existing technique.

High speed DNA sequencing accelerator using FPGA

This paper presents the development of High Speed DNA sequencing accelerator based on Smith-Waterman algorithm using FPGA. The scope of the paper focuses on speed optimization with parallelism. Smith-Waterman algorithm is sensitive algorithm used for procedure of DNA sequence alignments in computational molecular biology. As the number of sequence database increase exponentially, it affects the performance of Smith-Waterman algorithm in general purpose computer. Therefore, several techniques have been developed in order to speed up the crucial sequence comparison processes. Hence, optimization technique which used parallelism approach has been utilized. Moreover, the technique, which was previously used in cluster computing, has been exploited and implemented on FPGA technology. The potential of FPGAs implementation is vast in term of cost reduction, faster speed and parallelism. The design has been described using Verilog HDL and target to Altera Cyclone II 2C70. In this paper we introduce the new technique of DNA sequencing algorithm with 10 based pair DNA sequences been aligned at single clock cycle. The result of compilation consisting of 821 logic elements with total cell delay 10.472 ns and total interconnect delays 17.592 ns.

Improved data minimization technique in reducing memory space complexity for DNA local alignment accelerator application

Improved data minimization technique to optimize the length of DNA sequence and alignment result characters representation is presented in this paper. The primary objective is to improve and optimize data representation for DNA sequences alignment and result character. The proposed design change in algorithm and architecture is presented in this paper. Algorithm design based on binary equivalent method is used to obtain the optimal size of characters representation. The code is written, compiled and simulated using Altera Quartus II Version 9.0 EDA tools. Verilog Hardware Description Language (HDL) and Altera Cyclone II EP2C35 FPGA are used as coding language and target device respectively. In addition, the structural modelling technique is used to reduce the design complexity. Simulation result showed that the improved data minimization technique takes 50% more memory compared to previous work, but it covers 6 DNA sequences and alignment result characters.

Sequence alignment using systolic array for an accelerator

Performance and large memory space are the most prominent issues highlighted for local DNA sequences alignment. Therefore, this study is an attempt to test the systolic array approach for Smith-Waterman (SW) algorithm for improving the performance of DNA sequence alignment accelerator. The design was developed using LabVIEW and targeted to Xilinx Spartan 3E while the original SW has been used as a benchmark for performance comparison. Systolic array SW has recorded better performance as compared to original SW. Thus, by applying systolic array concept, it will improve the alignment performance whilst minimize the complexity of the design.

Design and development of DNA fragment assembly using IWP method

From time to time, researchers always try to improve algorithm for DNA fragment assembly that using de Bruijn graph. A de Bruijn graph is one of graph theoretical approach that based on short words (k-mers) that is ideal for high coverage, very short read (25-50bp) data sets. Therefore, the content of this paper proposed the development of DNA fragment assembly by using one of method that applied de Bruijn graph to construct complete a sequence, called Idury Waterman and Pevzner method. The algorithm was developed using Verilog HDL in Xilinx ISE Design Suite 14.2. The simulation used VCS Synopsys tool. The simulation result shows that it is tally with the theoretical analysis and was presented well in this paper.

Design and Analysis of High Performance and Low Power Matrix Filling for DNA Sequence Alignment Accelerator Using ASIC Design Flow

Efficient sequence alignment is one of the most important and challenging activities in bioinformatics. Many algorithms have been proposed to perform and accelerate sequence alignment activities. Among them Smith-Waterman (S-W) is the most sensitive (accurate) algorithm. This paper presents a novel approach and analysis of High Performance and Low Power Matrix Filling for DNA Sequence Alignment Accelerator by using ASIC design flow. The objective of this paper is to improve the performance of the DNA sequence alignment and to optimize power reduction of the existing technique by using Smith Waterman (SW) algorithm. The scope of study is by using the matrix filling method which is in parallel implementation of the Smith-Waterman algorithm. This method provides more efficient speed up compared to the traditional sequential implementation but at the same time maintaining the level of sensitivity. The methodology of this paper is using FPGA and Synopsis. This technique is used to implement the massive parallelism. The design was developed in Verilog HDL coding and synthesized by using LINUX tools. Matrix Cells with a design area 8808.307mm2 at 40ns clock period is the best design. Thus the power required at this clock period also smaller, dynamic power 111.1415uW and leakage power 212.9538 Nw. This is a large improvement over existing designs and improves data throughput by using ASIC design flow.

Design and Analysis of 8-bit Smith Waterman based DNA Sequence Alignment Accelerator's Core on ASIC Design Flow

This paper present the design and analysis of 8-bit Smith Waterman (SW) based DNA sequence alignment accelerators core on ASIC design flow. The objective of the project is to construct and analyse the core module that can perform the Smith Waterman algorithms operations, which are comparing, scoring and back tracing, using the technique used in (1,2) on ASIC design flow. Nowadays, the DNA and protein databases are increasing rapidly and these add new challenges to the current computing resources. New techniques, algorithms, designs, hardware and software that can maximize the computational speed, minimize the power and energy consumption, and boost the throughput need to be developed in order to meet the current and future requirements. In DNA sequence alignment process, the DNA sequences are compared using different alignment requirement techniques such as global alignment, local alignment, motif alignment and multiple sequence alignment. Moreover, there are several algorithms used to perform the sequence alignment process such as Needleman- Wunch algorithm, Smith Waterman algorithm, FASTA, BLAST and so on. For this paper, the focus is on local alignment using Smith Waterman algorithm. The design was modelled using Verilog and the functionality was verified using Xilinx and VCS. The RTL codes was mapped and synthesized to technology based logics using Design Compiler (DC). The cores layout was implemented using Place and Route tool, IC Compiler (ICC). Based on the results, the core design area was 2108.937620 um 2 .The maximum time constraints were 6.85 ns and 6.93 ns in ICC and PT. The minimum time constraints were 0.28 ns and 0.30 ns in ICC and PT respectively. In conclusion, the design had been successfully implemented on ASIC design flow. Moreover, the results showed that the design can be further optimized to work at faster speeds.

Capability of Indium Tin Oxide as a sensing mechanism for engine oil degradation monitoring

This paper presents the capabilities of glass Indium Tin Oxide (ITO) for engine oil degradation sensing monitoring system with resistive application. The glass ITO is a resistive material which has the ability to measure oil samples in resistive. This material is ideal with its durability and heat resistant characteristics. The characteristics of Indium Tin Oxide will be measured in voltage and resistance with suitable ROIC circuit interface. Aim for this research is to classify the resistance value with the same type engine oil with different lifespans. It is believe that this new type bulk resistive material can improve the oil degradation sensing in automotive application and cheaper manufacturing. A simple innovation system is constructed to provide oil conditioning in vehicle with implementing the small glass ITO at the end of the dipstick. This innovation is more precise way to determine the oil degradation with conditioning method.