Abhijeet Paul

Sidewall roughness and line profile measurement of photoresist and finFET features by cross-section STEM and TEM image for reference metrology

The novel method of sub-nanometer uncertainty for the line width measurement and the line profile measurement using STEM (Scanning Transmission Electron Microscope) images is proposed to calibrate CD-SEM line width measurement and the standardization of line profile measurement as reference metrology. In accordance with the proposed method, we already have established the methodology of profile of Si line and photoresist feature for reference metrology. In this article, we applied the proposed method to the sidewall roughness measurement of photoresist features and line profile measurement of finFET features. Using the proposed method, specimens of photoresist feature and finFET feature are sliced as thin specimens of 100 nm thickness by FIB (Focused Ion Beam) micro sampling system. Then the cross-sectional images of the specimens are obtained by STEM and TEM. The sidewall roughness of photoresist features is estimated by the maximum slope of the image intensity graph at the edge. Then, the sidewall roughness is also measured by CD-AFM (Critical Dimension Atomic Force Microscope); we compared the results by STEM image and CD-AFM. Moreover, the line profile of finFET features is defined using TEM images for reference metrology. We compared the line width of fin measured by the proposed method and CD value by CD-SEM measurement.

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.

Assessment of critical dimension small-angle x-ray scattering measurement approaches for FinFET fabrication process monitoring

Abstract. We have used synchrotron-based critical dimension small-angle x-ray scattering (CD-SAXS) to monitor the impact of hydrogen annealing on the structural characteristics of silicon FinFET structures fabricated using self-aligned double patterning on both bulk silicon and silicon-on-insulator (SOI) substrates. H2 annealing under different conditions of temperature and gas pressure allowed us to vary the sidewall roughness and observe the response in the two metrology approaches. In the case of the simpler bulk Si FinFET structures, the CD-SAXS measurements of the critical dimensions are in substantive agreement with the top–down critical dimension scanning electron microscopy metrology. Corresponding characterizations on SOI-based FinFET structures showed less agreement, which is attributed to the more complex structural model required for SOI FinFET CD-SAXS modeling. Because sidewall roughness is an important factor in the performance characteristics of Si FinFETs, we have compared the results of roughness measurements using both critical dimension atomic force microscopy (CD-AFM) and CD-SAXS. The measurements yield similar estimates of sidewall roughness, although the CD-AFM values were typically larger than those generated by CD-SAXS. The reasons for these differences will be discussed.

Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs

This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.

Metal Gate (TiN, TiC, TaN) Film Stack Stress

Successful stress engineering in semiconductor device structures must consider all the contributions to the stress field including those not typically considered for stress, such as work function metal (WFM) gate layers that are used to tune to the desired work function level. These films induce stress especially since they are so close to the channel region. In this study we measure stress from blanket layer films and combinations of TiN, TiC, and TaN deposited on Hf oxide, at thicknesses that are typically used for advanced metal–oxide–semiconductor field-effect transistor (MOSFET) devices. Tungsten (W) deposited on top of the WFM layer stacks is also measured. For combination film stacks, the stress is measured after each deposition step. The induced stress from the WFM is significant, in the range of hundreds of MPa, and varies according to the thickness and processing conditions such as annealing temperature and time, etc. Results from these blanket film measurements were used as a guide for technology computer-aided design (TCAD) modeling of the stress field in FinFET structures with design rules comparable to 10-nm technology. The tensor stress components identify areas of compressive and tensile stress and with a magnitude similar to expected results. The stress field could be used to calculate the FinFET device performance, and in this case an example is provided with the relative improvement in drain current.