Abner Bello

Sidewall roughness and line profile measurement of photoresist and finFET features by cross-section STEM and TEM image for reference metrology

The novel method of sub-nanometer uncertainty for the line width measurement and the line profile measurement using STEM (Scanning Transmission Electron Microscope) images is proposed to calibrate CD-SEM line width measurement and the standardization of line profile measurement as reference metrology. In accordance with the proposed method, we already have established the methodology of profile of Si line and photoresist feature for reference metrology. In this article, we applied the proposed method to the sidewall roughness measurement of photoresist features and line profile measurement of finFET features. Using the proposed method, specimens of photoresist feature and finFET feature are sliced as thin specimens of 100 nm thickness by FIB (Focused Ion Beam) micro sampling system. Then the cross-sectional images of the specimens are obtained by STEM and TEM. The sidewall roughness of photoresist features is estimated by the maximum slope of the image intensity graph at the edge. Then, the sidewall roughness is also measured by CD-AFM (Critical Dimension Atomic Force Microscope); we compared the results by STEM image and CD-AFM. Moreover, the line profile of finFET features is defined using TEM images for reference metrology. We compared the line width of fin measured by the proposed method and CD value by CD-SEM measurement.

Assessment of critical dimension small-angle x-ray scattering measurement approaches for FinFET fabrication process monitoring

Abstract. We have used synchrotron-based critical dimension small-angle x-ray scattering (CD-SAXS) to monitor the impact of hydrogen annealing on the structural characteristics of silicon FinFET structures fabricated using self-aligned double patterning on both bulk silicon and silicon-on-insulator (SOI) substrates. H2 annealing under different conditions of temperature and gas pressure allowed us to vary the sidewall roughness and observe the response in the two metrology approaches. In the case of the simpler bulk Si FinFET structures, the CD-SAXS measurements of the critical dimensions are in substantive agreement with the top–down critical dimension scanning electron microscopy metrology. Corresponding characterizations on SOI-based FinFET structures showed less agreement, which is attributed to the more complex structural model required for SOI FinFET CD-SAXS modeling. Because sidewall roughness is an important factor in the performance characteristics of Si FinFETs, we have compared the results of roughness measurements using both critical dimension atomic force microscopy (CD-AFM) and CD-SAXS. The measurements yield similar estimates of sidewall roughness, although the CD-AFM values were typically larger than those generated by CD-SAXS. The reasons for these differences will be discussed.

Metrology capabilities and needs for 7nm and 5nm logic nodes

This paper will provide a high level overview of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry, concentrating on logic applications. First, we will take a broad view of the needs of patterned defect, critical dimensional (CD/3D), overlay and films metrology, and present the extensive list of applications for which metrology solutions are needed. Commonalities and differences among the various applications will be shown. We will then report on the gating technical limits of the most important of these metrology solutions to address the metrology challenges of future nodes, highlighting key metrology technology gaps requiring industry attention and investment

7/5nm logic manufacturing capabilities and requirements of metrology

This paper will provide an update to previous works [2][4][9] to our view of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry, concentrating on logic technology for foundries. First, we will review of the needs of patterned defect, critical dimensional (CD/3D), overlay and films metrology, and present the extensive list of applications for which metrology solutions are needed. We will then update the industry’s progress towards addressing gating technical limits of the most important of these metrology solutions, highlighting key metrology technology gaps requiring industry attention and investment.

Hybrid enabled thin film metrology using XPS and optical

Complexity of process steps integration and material systems for next-generation technology nodes is reaching unprecedented levels, the appetite for higher sampling rates is on the rise, while the process window continues to shrink. Current thickness metrology specifications reach as low as 0.1A for total error budget – breathing new life into an old paradigm with lower visibility for past few metrology nodes: accuracy. Furthermore, for advance nodes there is growing demand to measure film thickness and composition on devices/product instead of surrogate planar simpler pads. Here we extend our earlier work in Hybrid Metrology to the combination of X-Ray based reference technologies (high performance) with optical high volume manufacturing (HVM) workhorse metrology (high throughput). Our stated goal is: put more “eyes” on the wafer (higher sampling) and enable move to films on pattern structure (control what matters). Examples of 1X front-end applications are used to setup and validate the benefits.

Copper process control with picosecond ultrasonic technology: A study

Copper topography control during the IC fabrication process is a critical process step as it maintains global planarity across the wafer. Die to die variations in Cu thickness occur during copper deposition and removal process at various metal levels. In this work, the challenges associated with obtaining good process control of Cu thickness using Metapulse tools is discussed. The stability and accuracy of the measurement recipe is analyzed and improved. It is seen that these improvements are directly correlated to reduced thickness variation thereby enabling tighter process control in advanced technologies.

XPS-XRF hybrid metrology enabling FDSOI process

Planar fully-depleted silicon-on-insulator (FDSOI) technology potentially offers comparable transistor performance as FinFETs. pFET FDOSI devices are based on a silicon germanium (cSiGe) layer on top of a buried oxide (BOX). Ndoped interfacial layer (IL), high-k (HfO2) layer and the metal gate stacks are then successively built on top of the SiGe layer. In-line metrology is critical in precisely monitoring the thickness and composition of the gate stack and associated underlying layers in order to achieve desired process control. However, any single in-line metrology technique is insufficient to obtain the thickness of IL, high-k, cSiGe layers in addition to Ge% and N-dose in one single measurement. A hybrid approach is therefore needed that combines the capabilities of more than one measurement technique to extract multiple parameters in a given film stack. This paper will discuss the approaches, challenges, and results associated with the first-in-industry implementation of XPS-XRF hybrid metrology for simultaneous detection of high-k thickness, IL thickness, N-dose, cSiGe thickness and %Ge, all in one signal measurement on a FDSOI substrate in a manufacturing fab. Strong correlation to electrical data for one or more of these measured parameters will also be presented, establishing the reliability of this technique.

Methodology to estimate TSV film thickness using a novel inline “adaptive pattern registration” method

A novel “adaptive pattern registration” method is developed which gives a reliable estimate of various film thickness in a wafer level TSV. The film thickness are measured using picosecond ultrasonic metrology technique. The adaptive pattern registration method provides higher measurement accuracy at reduced cycle time in comparison to Scanning White-Light Interferometry based technique. It will be shown that TaN/Ta (barrier), Cu Seed and Cu plating film thickness measured at wafer level correlates well to the film thickness at the infield TSV level. The effect of these film thickness on electrical performance of the TSVs will also be discussed.

Metal Gate (TiN, TiC, TaN) Film Stack Stress

Successful stress engineering in semiconductor device structures must consider all the contributions to the stress field including those not typically considered for stress, such as work function metal (WFM) gate layers that are used to tune to the desired work function level. These films induce stress especially since they are so close to the channel region. In this study we measure stress from blanket layer films and combinations of TiN, TiC, and TaN deposited on Hf oxide, at thicknesses that are typically used for advanced metal–oxide–semiconductor field-effect transistor (MOSFET) devices. Tungsten (W) deposited on top of the WFM layer stacks is also measured. For combination film stacks, the stress is measured after each deposition step. The induced stress from the WFM is significant, in the range of hundreds of MPa, and varies according to the thickness and processing conditions such as annealing temperature and time, etc. Results from these blanket film measurements were used as a guide for technology computer-aided design (TCAD) modeling of the stress field in FinFET structures with design rules comparable to 10-nm technology. The tensor stress components identify areas of compressive and tensile stress and with a magnitude similar to expected results. The stress field could be used to calculate the FinFET device performance, and in this case an example is provided with the relative improvement in drain current.