Abhijit Asati

A high-speed, hierarchical 16×16 array of array multiplier design

Array multipliers are preferred for smaller operand sizes due to their simpler VLSI implementation, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are less suitable for VLSI implementation since, being less regular, they require larger total routing length, which may degrade their performance. Some hybrid architectures called ‘array of array’ multipliers have intermediate performance. These multipliers have a time complexity better than array multipliers, and therefore becomes an obvious choice for higher performance multiplier designs of moderate operand sizes. In this paper a 16×16 unsigned ‘array of array’ multiplier circuit is designed with hierarchical structure and implemented using conventional CMOS logic in 0.6µm, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS. The proposed multiplier implementation shows large reduction in propagation delay and the average power consumption (at 20MHz) as compared to 16-bit Booth encoded Wallace tree multiplier by F Jalil [3]. The total transistor count, maximum instantaneous power, leakage power, core area, total routing length and number of vias are also presented.

An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style

The Array multipliers are generally preferred for smaller operand sizes due to their simpler VLSI implementations, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are unsuitable for VLSI implementation since they require larger total routing length, which may degrade performance. The properties of simpler VLSI implementation can be combined with fully pipelined circuit design using CMOS TSPC (true single phase clock) logic design style to improve throughput of array multipliers. In this paper an improved high speed, fully pipelined 8times8 signed Baugh Wooley multiplier circuit has been designed and implemented using CMOS TSPC logic in 0.6 mum, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS utilizing optimized TSPC logic cells. The simulation results after parasitic extraction show that the inputs can be applied every clock and it can produce correct output after 17 clock cycles at 500 MHz clock rate. Thus the throughput of 500times106 multiplication per second is achieved using TSPC based fine grain pipelining. By designing and using novel TSPC full adder cell, our Baugh Wooley multiplier implementation shows large reduction in transistor count, average power and delay as compared to an implementation by Robert Rogenmoser and Qiuting Huang. The total transistor count, average power and maximum instantaneous power are indicated in comparison table.

A Novel Redundant Binary Number to Natural Binary Number Converter

Redundant binary number appears to be appropriate for high-speed arithmetic operation, but the delay and hardware cost associated with the conversion from redundant binary (RB) to natural binary (NB) number is still a challenging task. In the present investigation a simple approach has been adopted to achieve high speed with lesser hardware and power saving. A circuit level approach has been adopted to implement the equivalent bit conversion algorithm (EBCA) (Kim et al. IEEE Journal of Solid State Circuits 36:1538-1544, 2001, 38:159-160, 2003) for RB to NB conversion. The circuit is designed based on exploration of predictable carry out feature of EBCA algorithm. This implementation concludes a significant delay power product and component complexity advantage for a 64-bit RB to NB conversion using novel carry-look-ahead equivalent bit converter.

Generic modified Baugh Wooley multiplier

In this paper the structural pattern required to create a generic HDL code for a fast Baugh Wooley multiplier has been described. The ripple carry adder in the final stage of the conventional Baugh Wooley multiplier was replaced by a Linear Carry Select Adder, resulting in a modified Baugh Wooley architecture. The post-synthesis results of the multiplier architecture generated by the synthesis tool for HDL defined multiplication statement was compared with the synthesis results of conventional and as well as the modified Baugh Wooley multipliers for different operand sizes ranging from N=4 to N=60 using 90 nm technology library. The post synthesis results for characteristic parameters such as propagation delay, area and power consumption are compared. The comparison shows that the modified Baugh Wooley architecture is faster than the conventional architecture and the architecture generated by the synthesis tool for HDL defined multiplication statement. The speed improvement becomes significant for larger operand sizes.

Iris localization based on integro-differential operator for unconstrained infrared iris images

Iris localization is an important step for high accuracy iris recognition systems and it becomes difficult for iris images captured in unconstrained environments. The proposed method localizes irises in unconstrained infrared iris images having non-ideal issues such as severe reflections, eyeglasses, low contrast, low illumination and occlusions by eyebrow hair, eyelids and eyelashes. In the proposed method, the iris image is first preprocessed using morphological operation to remove reflections and make it suitable for subsequent steps. The proposed method detects pupil using Daugmans integro-differential operator (IDO) and iriss outer boundary is detected using proposed modified Daugmans IDO. The proposed method proposes a technique based on thresholding and morphological operation to reduce the number of pixels on which the IDO is applied for detecting pupil which improves the time performance and accuracy as well. The method was tested with CASIA-Iris-Thousand, version 4.0 (CITHV4) iris database which contains challenging images having non-ideal issues as described before. The average accuracy of the proposed method is 99.3% and average time cost per image is 1.86 seconds for CITHV4. The proposed method shows improvement in both accuracy and time when compared with some published state-of-the-art iris localization methods in the literature.

A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images

Iris segmentation in the iris recognition systems is a challenging task under noncooperative environments. The iris segmentation is a process of detecting the pupil, iris’s outer boundary, and eyelids in the iris image. In this paper, we propose a pupil localization method for locating the pupils in the non-close-up and frontal-view iris images that are captured under near-infrared (NIR) illuminations and contain the noise, such as specular and lighting reflection spots, eyeglasses, nonuniform illumination, low contrast, and occlusions by the eyelids, eyelashes, and eyebrow hair. In the proposed method, first, a novel edge-map is created from the iris image, which is based on combining the conventional thresholding and edge detection based segmentation techniques, and then, the general circular Hough transform (CHT) is used to find the pupil circle parameters in the edge-map. Our main contribution in this research is a novel edge-map creation technique, which reduces the false edges drastically in the edge-map of the iris image and makes the pupil localization in the noisy NIR images more accurate, fast, robust, and simple. The proposed method was tested with three iris databases: CASIA-Iris-Thousand (version 4.0), CASIA-Iris-Lamp (version 3.0), and MMU (version 2.0). The average accuracy of the proposed method is 99.72% and average time cost per image is 0.727?sec.

A Purely MUX Based High Speed Barrel Shifter VLSI Implementation Using Three Different Logic Design Styles

Barrel shifter is one of the important data path elements and widely used in many key computer operations from address decoding to computer arithmetic, using basic operations like data shifting and rotation. In this paper MUX based barrel shifter circuits are designed and implemented in 0.6μm, N-well CMOS process using three different logic design styles, namely, optimized static CMOS, transmission gate (TG) CMOS and dual rail domino CMOS logic. The proposed barrel shifter architecture implementation shows large reduction in the propagation delay, while keeping the almost similar average power consumption as compared to the implementation by Ramin Rafati [10]. A further inter comparison of implementations using three different logic design styles for various performance and characteristic parameters like circuit delay, average power, maximum instantaneous power, leakage Power, transistor count, layout core area, total routing length and number of via are presented.

Low-latency median filter core for hardware implementation of 5 × 5 median filtering

This study presents hardware implementation of 5 × 5 median filter that uses a new low-latency median filter (LLMF) core in order to find the median of 25 integer values. The proposed LLMF core architecture computes the median of 25 integers in just three clock cycles. The maximum frequency of operation of the proposed median filter architecture is 394 MHz on the Xilinx Zynq FPGA device. The proposed LLMF core provides reduced clock cycle latency compared with the existing state-of-the-art median filter core architectures.

Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow

Partitioning and scheduling of dataflow graphs(DFGs) has been a matter of extensive research for ASIC based development. With the advent of partial reconfigurable hardware the need to schedule DFGs with restricted resources is required. In this research we test and extend the conventional scheduling algorithm suited for reconfiguration. In algorithm we restrict the flow as offered by Xilinx in PR design. The performance of such flow should be much significant than the conventional software execution flow. Hence we estimate the timing comparison of the software and the hardware flow.

Hardware software co-design using profiling and clustering

The digital system design process can be accelerated by concurrent design of hardware and software. This process requires the migration of functions that are computational extensive to hardware. This paper presents a framework for identifying such functions by proposing an algorithm. The framework uses the time profiling and clustering technique to achieve the objectives. Open source spark compiler has been used to convert functions to hardware description language The final interfacing has been done in embedded development kit.