Anu Gupta

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.

On-chip resistors can make a stable current reference

A number of designs have been proposed for completely on-chip reference current generation but suffer varying degrees of drawbacks. The author presents a new design that provides a robust on-chip current reference circuit for submicron technologies without the usual disadvantages.

A Novel Redundant Binary Number to Natural Binary Number Converter

Redundant binary number appears to be appropriate for high-speed arithmetic operation, but the delay and hardware cost associated with the conversion from redundant binary (RB) to natural binary (NB) number is still a challenging task. In the present investigation a simple approach has been adopted to achieve high speed with lesser hardware and power saving. A circuit level approach has been adopted to implement the equivalent bit conversion algorithm (EBCA) (Kim et al. IEEE Journal of Solid State Circuits 36:1538-1544, 2001, 38:159-160, 2003) for RB to NB conversion. The circuit is designed based on exploration of predictable carry out feature of EBCA algorithm. This implementation concludes a significant delay power product and component complexity advantage for a 64-bit RB to NB conversion using novel carry-look-ahead equivalent bit converter.

Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs

This paper proposes a new high speed ternary full adder (TFA) cell for carbon nano tube field effect transistor (CNTFET) technology. The proposed design has a symmetric pull-up and pull-down networks along with a resistive voltage divider as its integral part, which is configured using transistors. The design takes inputs through a decoding unit and uses ternary nature of A & B but inherent binary nature of Cin leading to simplicity in design. The design demonstrates high driving power and robustness in terms of insusceptibility to voltage and temperature variations. The sum generation unit of proposed design is further modified for achieving an energy efficient three-input ternary XOR circuit which can be used as a basic cell in modern circuit design. Hspice simulation results with 32nm Stanford CNTFET model show 49% reduction in delay with 19% progress in power-delay product (PDP) for the proposed TFA and 43% reduction in delay with 48 % improvement in PDP for the proposed three input ternary XOR circuit in comparison with the CNTFET-based designs, recently published in the literature.

Iris localization based on integro-differential operator for unconstrained infrared iris images

Iris localization is an important step for high accuracy iris recognition systems and it becomes difficult for iris images captured in unconstrained environments. The proposed method localizes irises in unconstrained infrared iris images having non-ideal issues such as severe reflections, eyeglasses, low contrast, low illumination and occlusions by eyebrow hair, eyelids and eyelashes. In the proposed method, the iris image is first preprocessed using morphological operation to remove reflections and make it suitable for subsequent steps. The proposed method detects pupil using Daugmans integro-differential operator (IDO) and iriss outer boundary is detected using proposed modified Daugmans IDO. The proposed method proposes a technique based on thresholding and morphological operation to reduce the number of pixels on which the IDO is applied for detecting pupil which improves the time performance and accuracy as well. The method was tested with CASIA-Iris-Thousand, version 4.0 (CITHV4) iris database which contains challenging images having non-ideal issues as described before. The average accuracy of the proposed method is 99.3% and average time cost per image is 1.86 seconds for CITHV4. The proposed method shows improvement in both accuracy and time when compared with some published state-of-the-art iris localization methods in the literature.

A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images

Iris segmentation in the iris recognition systems is a challenging task under noncooperative environments. The iris segmentation is a process of detecting the pupil, iris’s outer boundary, and eyelids in the iris image. In this paper, we propose a pupil localization method for locating the pupils in the non-close-up and frontal-view iris images that are captured under near-infrared (NIR) illuminations and contain the noise, such as specular and lighting reflection spots, eyeglasses, nonuniform illumination, low contrast, and occlusions by the eyelids, eyelashes, and eyebrow hair. In the proposed method, first, a novel edge-map is created from the iris image, which is based on combining the conventional thresholding and edge detection based segmentation techniques, and then, the general circular Hough transform (CHT) is used to find the pupil circle parameters in the edge-map. Our main contribution in this research is a novel edge-map creation technique, which reduces the false edges drastically in the edge-map of the iris image and makes the pupil localization in the noisy NIR images more accurate, fast, robust, and simple. The proposed method was tested with three iris databases: CASIA-Iris-Thousand (version 4.0), CASIA-Iris-Lamp (version 3.0), and MMU (version 2.0). The average accuracy of the proposed method is 99.72% and average time cost per image is 0.727?sec.

Design of content-addressable memory cell using CNTFETs

This letter presents a design of three-valued content-addressable memory (3CAM) cell with low capacitance comparison logic using carbon nanotube field-effect transistors (CNTFETs). By utilising Synopsis HSPICE and latest layout design tools for 32 nm CNTFET, it is shown that the proposed 3CAM cell achieves 65% reduction in search delay and 6% saving in cell area with no loss of power in comparison with CNTFET-based 3CAM cell recently proposed in the literature.

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

ABSTRACT This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.

A comparative analysis of power and delay optimise digital logic families for high performance system design

In this paper, we propose a high performance system design methodology taking the best average delay on prime. Our analysis method is based on the commonly used logical effort methodology, extended to the least delay to find the transistors sizing. Simulation results are tabulated using SPECTRE in 0.18 µm CMOS technology as applied to three different logic styles including static CMOS, pseudo-NMOS and skewed logic. We observe that NAND based pseudo-NMOS logic design having NMOS width as 1 µm exhibits least delay but with enormous power dissipation, evaluated by the tool, whereas, skewed logic style response is better in terms of total power. Thus, the method used accurately shows the trade-off in power-delay of a given circuit, allowing a designer to choose the most appropriate logic style.

Low Power Cascaded Three Stage Amplifier with Multipath Nested Miller Compensation

This paper proposes a design for a low power cascaded three stage Operational Amplifier, with frequency compensation by Nested Miller Compensation which could be made to operate at low voltage supplies. The multipath technique is used to increase the bandwidth by converting the system into a two stage amplifier at high frequencies. The Op-Amp is designed in 180 nm technology and operates at a 3V power supply with a gain of 115 dB, bandwidth of 103 Mhz, phase margin of 45 degrees and a settling time of 80-90 ns. Graph and simulation results are provided to verify the performance and to demonstrate the advantages of this three stage cascaded topology.