Abhijit Biswas

Modeling of threshold voltage and subthreshold slope of nanoscale DG MOSFETs

Two-dimensional (2D) analytical models for the threshold voltage and subthreshold slope of fully depleted symmetric double gate (DG) n-MOSFETs have been presented in this paper. 2D Poissons equation has been solved with suitable boundary conditions to obtain the surface potential at the Si/SiO2 interface. The minimum surface potential has been employed to derive analytical expressions for the threshold voltage and subthreshold slope. Also, these expressions have been modified taking into account the effect of bandgap narrowing due to heavy channel doping and quantum-mechanical effects. In addition, the 2D numerical simulation results obtained using the device simulator ATLAS for the surface potential, the threshold voltage and subthreshold slope have been presented. Further our analytical data have been compared with numerical simulation results for various DG MOSFETs, and our analytical simulation results have also been compared with reported experimental data in the literature. A good agreement is observed among the three, ensuring the validity of our present model. The proposed model is simple and makes it easy to understand the influence of physical phenomena such as quantum-mechanical effects on the electrical parameters, such as the threshold voltage, compared to other models published elsewhere.

Equivalent circuit models of quantum cascade lasers for SPICE simulation of steady state and dynamic responses

The electrical equivalent circuits of quantum cascade lasers (QCLs) under steady state and under an ac small-signal are developed by employing simplified rate equations for electronic transitions between two levels and the rate equation for photon numbers. Two interactive circuits represent the steady state behaviour and another two coupled circuits model the ac small-signal performance of a QCL. The equivalent circuits are then used for SPICE simulation. The steady state equivalent circuit reproduces the light current curve of QCLs. The ac equivalent circuit yields the intensity modulation response, which matches almost exactly with the curve obtained from reported numerical calculations based on a third-order system model. In addition, the ac model is employed for SPICE simulation to give values of the modulation bandwidth for different values of photon lifetime. The SPICE model gives a slightly different curve for the bandwidth against photon lifetime from the curve plotted using the approximate analytical expression.

Modelling of threshold voltage and subthreshold slope of strained-Si MOSFETs including quantum effects

In this paper, the threshold voltage and subthreshold slope of strained-Si channel n-MOSFETs are determined, taking into account quantum-mechanical effects, and the effect of bandgap narrowing due to heavy channel doping and the effect of surface roughness at the Si/SiGe heterointerface for ultra thin channels. Quantum-mechanical effects have been incorporated by considering three components, (1) the modified subband energy of 2D inversion layer charges at the silicon dioxide–silicon interface, (2) the increased effective oxide thickness and (3) the altered value of ground state energy due to surface roughness. The analytical results of threshold voltage and threshold voltage difference are presented with reference to unstrained-Si channel for strained-Si MOSFETs by employing poly-Si gate and titanium nitride gate, the work function of which can be varied over a wide range. In addition, we have predicted the dependence of threshold voltage on different values of oxide thickness, channel doping concentration, and on the molar content, x, of Ge in the Si1−xGex virtual substrate. When compared with the theoretical data of Nayfeh et al our analytical results agree more closely with our experimental results and also with measured and simulated data of threshold voltage for a wide range of devices available in the literature. Furthermore, we have calculated the subthreshold slope of strained-Si channel MOSFETs for different amounts of Ge in the SiGe layer.

Effects of gate bias on the threshold voltage of nanoscale double gate MOSFETs

We have investigated the influence of gate bias voltage, applied to one of the two gates of the dual gate (DG) MOSFET, on the threshold voltage for different geometric dimensions, gate materials and drain to source voltage. In our studies we have employed the 2-D numerical device simulator ATLAS to determine the threshold voltage pertaining to DG MOSFETs. It is observed that the gate bias plays an important role in modifying the threshold voltage of DG MOSFETs and the threshold voltage increases with more negative values of gate bias for n-channel DG MOSFETs.

Effect of heat treatment duration on tribological behavior of electroless Ni-(high)P coatings

Electroless nickel coating occurs through an autocatalytic chemical reaction and without the aid of electricity. From tribological perspective, it is recommended due to its high hardness, wear resistance, lubricity and corrosion resistance properties. In this paper electroless Ni-P coatings with high phosphorous weight percentages are developed on mild steel (AISI 1040) substrates. The coatings are subjected to heat treatment at 300°C and 500°C for time durations up to 4 hours. The effect of heat treatment duration on the hardness as well as tribological properties is discussed in detail. Hardness is measured in a micro hardness tester while the tribological tests are carried out on a pin-on-disc tribotester. Wear is reported in the form of wear rates of the sample subjected to the test. As expected, heat treatment of electroless Ni-P coating results in enhancement in its hardness which in turn increases its wear resistance. The present study also finds that duration of heat treatment has quite an effect on the properties of the coating. Increase in heat treatment time in general results in increase in the hardness of the coating. Coefficient of friction is also found to be lesser for the samples heat treated for longer durations (4 hour). However, in case of wear, similar trend is not observed. Instead samples heat treated for 2 to 3 hour display better wear resistance compared to the same heat treated for 4 hour duration. The microstructure of the coating is also carried out to ensure about its proper development. From scanning electron microscopy (SEM), the coating is found to possess the conventional nodular structure while energy dispersive X-ray analysis (EDX) shows that the phosphorous content in the coating to be greater than 9%. This means that the current coating belongs to the high phosphorous category. From X-ray diffraction analysis (XRD), it is found that coating is amorphous in as-deposited condition but transforms into a crystalline structure with heat treatment.