Peter Verheyen

High-efficiency fiber-to-chip grating couplers realized using an advanced CMOS-compatible Silicon-On-Insulator platform

A new generation of Silicon-on-Insulator fiber-to-chip grating couplers which use a silicon overlay to enhance the directionality and thereby the coupling efficiency is presented. Devices are realized on a 200 mm wafer in a CMOS pilot line. The fabricated fiber couplers show a coupling efficiency of -1.6 dB and a 3 dB bandwidth of 80 nm.

Silicon-organic hybrid (SOH) IQ modulator using the linear electro-optic effect for transmitting 16QAM at 112 Gbit/s

Advanced modulation formats call for suitable IQ modulators. Using the silicon-on-insulator (SOI) platform we exploit the linear electro-optic effect by functionalizing a photonic integrated circuit with an organic χ(2)-nonlinear cladding. We demonstrate that this silicon-organic hybrid (SOH) technology allows the fabrication of IQ modulators for generating 16QAM signals with data rates up to 112 Gbit/s. To the best of our knowledge, this is the highest single-polarization data rate achieved so far with a silicon-integrated modulator. We found an energy consumption of 640 fJ/bit.

Performance tradeoff between lateral and interdigitated doping patterns for high speed carrier-depletion based silicon modulators

Carrier-depletion based silicon modulators with lateral and interdigitated PN junctions are compared systematically on the same fabrication platform. The interdigitated diode is shown to outperform the lateral diode in achieving a low VπLπ of 0.62 V∙cm with comparable propagation loss at the expense of a higher depletion capacitance. The low VπLπ of the interdigitated PN junction is employed to demonstrate 10 Gbit/s modulation with 7.5 dB extinction ration from a 500 µm long device whose static insertion loss is 2.8 dB. In addition, up to 40 Gbit/s modulation is demonstrated for a 3 mm long device comprising a lateral diode and a co-designed traveling wave electrode.

An octave-spanning mid-infrared frequency comb generated in a silicon nanophotonic wire waveguide

Laser frequency combs, sources with a spectrum consisting of hundred thousands evenly spaced narrow lines, have an exhilarating potential for new approaches to molecular spectroscopy and sensing in the mid-infrared region. The generation of such broadband coherent sources is presently under active exploration. Technical challenges have slowed down such developments. Identifying a versatile highly nonlinear medium for significantly broadening a mid-infrared comb spectrum remains challenging. Here we take a different approach to spectral broadening of mid-infrared frequency combs and investigate CMOS-compatible highly nonlinear dispersion-engineered silicon nanophotonic waveguides on a silicon-on-insulator chip. We record octave-spanning (1,500–3,300 nm) spectra with a coupled input pulse energy as low as 16 pJ. We demonstrate phase-coherent comb spectra broadened on a room-temperature-operating CMOS-compatible chip.

Exploring the limits of stress-enhanced hole mobility

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

Demonstration of silicon-on-insulator mid-infrared spectrometers operating at 3.8 um

The design and characterization of silicon-on-insulator mid-infrared spectrometers operating at 3.8 μm is reported. The devices are fabricated on 200 mm SOI wafers in a CMOS pilot line. Both arrayed waveguide grating structures and planar concave grating structures were designed and tested. Low insertion loss (1.5-2.5 dB) and good crosstalk characteristics (15-20 dB) are demonstrated, together with waveguide propagation losses in the range of 3 to 6 dB/cm.

Layout impact on the performance of a locally strained PMOSFET

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L/sub s/d/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

Successful Selective Epitaxial Si1 − x Ge x Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Si 1-x Ge x /Si heterostructures are useful for numerous device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si 1-x Ge x has some advantages compared to a nonselective growth process. However, some issues such as thickness nonuniformity (microloading on a micrometer scale and gas depletion on a wafer scale) and facet formation must be solved. In this paper, we give a detailed overview of our selective Si 1-x Ge x growth process in a standard production-oriented chemical vapor deposition system for Go contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content (no microloading) and with a wafer scale layer nonuniformity that is better than the accuracy of the measurement techniques (∼2%). Facet formation was avoided by choosing the correct growth conditions and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristies. The layer quality is further demonstrated by the performance of Si 1-x Ge x heterojunction bipolar transistors (0.35 and 0.25 μm technology), and p-type Si 1-x Ge x heterojunction metal oxide semiconductor devices (effective gate length down to 70 nm).

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes

Silicon-on-Insulator Polarization Rotator Based on a Symmetry Breaking Silicon Overlay

We demonstrate a polarization rotator fabricated using a 4 etch-step complementary metal-oxide-semiconductor (CMOS)-compatible process including layer depositions on a silicon-on-insulator wafer. The measured polarization rotation efficiency is over a wavelength range of 80 nm. A robustness investigation shows that the design is compatible with CMOS fabrication capabilities.