Abhinav Kranti

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Device Design and Estimated Performance for p-Type Junctionless Transistors on Bulk Germanium Substrates

The junctionless nanowire transistor (JNT) has recently been demonstrated to be a promising device for sub-20-nm nodes. So far, most devices were made on semiconductor-on-insulator substrates. The aim of this work is to evaluate the concept of multigate germanium (Ge) JNTs on bulk substrates, using a dedicated modeling methodology. The variation of device performance due to geometry, channel, and substrate doping concentrations is discussed and proposed as a guideline for designing p-type Ge bulk JNTs. This work shows that a potential barrier is formed in the substrate by the p-n junction that isolates the channel from the substrate, and an effective confinement of current in the nanowire can be achieved. The Ge bulk JNT facilitates excellent scalability. Our modeling predicts that, for a gate length of 16 nm, a subthreshold slope of 77 mV/dec and a drain-induced barrier lowering of 70 mV can be obtained with an <formula formulatype=inline><tex Notation=TeX>

Volume accumulated double gate junctionless MOSFETs for low power logic technology applications

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Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

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Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

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Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs

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The work highlights the potential benefits of operating Junctionless (JL) Double Gate (DG) MOSFETs in the volume accumulation mode. An optimized 20 nm JL MOSFET in volume accumulation achieves impressive intrinsic delay value of 9 ps and on-off current ratio of ~106 at a gate and drain bias of 0.4 V (subthreshold region). These values are significantly better than traditional JL MOSFETs designed with higher doping concentration (≥ 1019 cm-3). The maximum sensitivity of threshold voltage is limited to 3.5% for a 10% change in device parameters. The constraints for gate workfunction are less stringent in volume accumulated JL MOSFETs. A JL 6T-SRAM cell achieves an impressive read and hold noise margins of 156 mV and 364 mV along with a write-ability current of 20 μA at a supply voltage of 0.8 V. The paper presents new viewpoints for the design and optimization of junctionless transistors and circuits for low power logic technology applications.

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In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ∼2 s at a temperature of 85u2009°C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory.

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We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time (RT) of ~1.5 s at 85°C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125°C).

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The paper investigates the impact of doping concentration on the performance of Ultra Low Power (ULP) Junctionless Double Gate MOSFETs. Results show that intrinsic delay is reduced by 69% and on-off current ratio is increased by 2.5 times when junctionless transistors are designed with a doping concentration of 5×10¹⁸ cm^-3 as compared to those designed with 3×10¹⁹ cm^-3. Additional advantage of operating at 5×10¹⁸ cm^-3 is the significant reduction in the parameter sensitivity values of on-current, off-current and intrinsic delay. JL devices exhibit least sensitivity towards gate length in comparison to other parameters. The results when compared with inversion mode and under lap devices highlight the advantages of junctionless devices for ULP logic technology applications.