Mukta Singh Parihar

Bipolar effects in unipolar junctionless transistors

In this work, we analyze hysteresis and bipolar effects in unipolar junctionless transistors. A change in subthreshold drain current by 5 orders of magnitude is demonstrated at a drain voltage of 2.25 V in silicon junctionless transistor. Contrary to the conventional theory, increasing gate oxide thickness results in (i) a reduction of subthreshold slope (S-slope) and (ii) an increase in drain current, due to bipolar effects. The high sensitivity to film thickness in junctionless devices will be most crucial factor in achieving steep transition from ON to OFF state.

Revisiting the doping requirement for low power junctionless MOSFETs

In this work, we revisit the requirement of higher channel doping (≥1019 cm−3) in junctionless (JL) double gate MOSFETs. It is demonstrated that moderately doped (1018 cm−3) ultra low power (ULP) JL transistors perform significantly better than heavily doped (1019 cm−3) devices. JL MOSFETs with moderate doping results in the spreading out of carriers across the entire silicon film instead of being localized at the center of the film. This improves gate controllability leading to higher on–off current ratio and lower intrinsic delay for ULP subthreshold logic applications. Additional benefits of using a channel doping concentration of 1018 cm−3 instead of conventional heavily doped design is the significant reduction in threshold voltage sensitivity values (by ~70–90%) with respect to film thickness and gate oxide thickness. Further improvement in ULP performance metrics can be achieved by limiting the source/drain implantation away from the gate edge. This design, specifically for ULP, allows the requirement of gate workfunction to be reduced from p+-poly (~ 5.1 eV) to near about midgap values (~ 4.8 eV). On–off current ratio and intrinsic delay for optimized JL devices are compared for low standby power projections of the technological roadmap. A 6T-SRAM cell operating at 0.8 V with 25 nm JL devices exhibits a static noise margin of 151 mV with gate workfunction offset of 0.2 eV with respect to midgap value (4.72 eV). The results highlight new viewpoints for realizing improved low power JL transistors.

Single transistor latch phenomenon in junctionless transistors

In this work, we report on the single transistor latch phenomenon in junctionless transistors. In the latch condition, the device is unable to turn-off despite a reduction in gate bias. It is shown that impact ionization induced latch condition can occur due to an increase in drain bias, silicon film thickness, gate oxide thickness, and doping concentration. The latch phenomenon is explained in terms of generation–recombination rates, electrostatic potential, electric field distribution and product of current density and electric field (J·E). As latch condition is undesirable for dynamic memory applications, the work highlights the significance of (J·E) as a performance metric to avoid the junctionless transistor being driven into the latch mode.

Bipolar snapback in junctionless transistors for capacitorless dynamic random access memory

In this work, we analyze the snapback effect and extract the effective bipolar current gain in junctionless nanotransistors. The optimal electron and hole concentrations required to trigger and sustain bipolar snapback in junctionless transistors have been evaluated. The occurrence of snapback at lower drain bias (≅ 2 V) in junctionless devices in comparison to conventional inversion mode transistors demonstrates the enormous potential for static power reduction in capacitorless dynamic random access memories. High values (40–70) of effective bipolar current gain achieved in optimally designed junctionless transistors can be utilized to improve the sensing margin for dynamic memories.

Volume accumulated double gate junctionless MOSFETs for low power logic technology applications

The work highlights the potential benefits of operating Junctionless (JL) Double Gate (DG) MOSFETs in the volume accumulation mode. An optimized 20 nm JL MOSFET in volume accumulation achieves impressive intrinsic delay value of 9 ps and on-off current ratio of ~106 at a gate and drain bias of 0.4 V (subthreshold region). These values are significantly better than traditional JL MOSFETs designed with higher doping concentration (≥ 1019 cm-3). The maximum sensitivity of threshold voltage is limited to 3.5% for a 10% change in device parameters. The constraints for gate workfunction are less stringent in volume accumulated JL MOSFETs. A JL 6T-SRAM cell achieves an impressive read and hold noise margins of 156 mV and 364 mV along with a write-ability current of 20 μA at a supply voltage of 0.8 V. The paper presents new viewpoints for the design and optimization of junctionless transistors and circuits for low power logic technology applications.

Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications

In the present work, we demonstrate the potential of double gate junctionless (JL) architecture for enhanced sensitivity for detecting biomolecules in cavity modulated field effect transistors (FETs). The higher values of body factor, achieved in asymmetric gate operation under impact ionization is utilized for enhanced sensing margin which is nearly five times higher than compared to symmetrical mode operation. The intrinsic detection sensitivity is evaluated in terms of threshold voltage change, and the ratio of drain current in the presence and absence of biomolecules in JL nanotransistors. It is shown that asymmetric mode JL transistor achieves a higher degree of detection sensitivity even for a partially filled cavity. The work demonstrates the potential of JL channel architecture for cavity based dielectric modulated FET biosensors.

Back bias induced dynamic and steep subthreshold swing in junctionless transistors

In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of −0.9 V, achieves over 5 orders of change in drain current at a gate overdrive of 200 mV and drain bias of 1 V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias.

Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs

The paper investigates the impact of doping concentration on the performance of Ultra Low Power (ULP) Junctionless Double Gate MOSFETs. Results show that intrinsic delay is reduced by 69% and on-off current ratio is increased by 2.5 times when junctionless transistors are designed with a doping concentration of 5×10¹⁸ cm^-3 as compared to those designed with 3×10¹⁹ cm^-3. Additional advantage of operating at 5×10¹⁸ cm^-3 is the significant reduction in the parameter sensitivity values of on-current, off-current and intrinsic delay. JL devices exhibit least sensitivity towards gate length in comparison to other parameters. The results when compared with inversion mode and under lap devices highlight the advantages of junctionless devices for ULP logic technology applications.

Occurrence of zero gate oxide thickness coefficient in junctionless transistors

In this paper, we report on the occurrence of Zero Gate Oxide Thickness Coefficient (ZToxC) in junctionless transistors. It is shown that due to bipolar effects, drain current increases with an increase in oxide thickness up to a certain gate voltage (VZToxC), whereas beyond (VZToxC), current follows the conventional transistor theory and reduces with an increment in gate oxide thickness. These two different trends lead to a condition of drain current being independent of oxide thickness at the gate bias corresponding to VZToxC. The occurrence of ZToxC classifies the predominant conduction mechanism into bipolar or unipolar mode in junctionless transistors.

Optimizing nanoscale MOSFET architecture for low power analog/RF applications

This work reports on possible ways of improving analog/RF performance metrics, through device structure optimization, for low power applications. It is shown that underlap source/drain (S/D) design and junctionless transistor architecture can both yield improved analog/RF figures of merit in comparison to conventional abrupt source/drain MOSFETs. Junctionless devices overcome the gain-bandwidth trade-off associated with analog design. The results are significant for RFICs in emerging ultra-low-power technologies.