Abhirup Lahiri

A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

This paper presents a 32 kHz input and 960 MHz output low-power charge-pump phase-locked loop (CP-PLL) with a novel dual-path loop-filter for resistor noise reduction technique. The resistor noise reduction technique using dual-path loop-filter involves no “additional” active component; area/power overhead compared to the conventional CP-PLL. Reverse sub-threshold leakage compensated source-switched charge-pump (SS-CP) is employed in the PLL for improved reference spur performance. The PLL with minimum analog supply voltage of 1.62 V and minimum digital supply voltage of 0.65 V; with die area of 0.15 mm 2 is designed and fabricated in 28 nm STMicroelectronics FD-SOI process. The silicon measurement results have been included and the PLL performance includes total integrated jitter of 530 ps, reference spur of -65 dBc and current consumption of 600 μA.

A 140µA 34ppm/°C 30MHz Clock Oscillator in 28nm CMOS Bulk Process

This paper presents a 30MHz ring based clock oscillator in 28nm CMOS bulk process embedded in a negative feedback loop achieving 0.57% peak-to-peak temperature spread (worst case process corners) from - 40°C to 125°C and consuming 140μA current from 1.8V regulated voltage supply. Since the oscillation frequency of the ring oscillator is locked to Icomp/(C*Vref) by the loop, the bias current (Icomp) and voltage (Vref) can be independently temperature compensated to achieve very low temperature spread of the frequency in our implementation. The presented design achieves a temperature spread which is 10x lower than conventional RC oscillator in spite of high temperature coefficient (363 ppm/°C) of precision resistor available in the technology and absence of complementary temperature coefficient resistors. SPICE simulation results of the designed oscillator in 28nm CMOS bulk process along with performance summary and comparisons with other works have been included.

Digital LDO with analog-assisted dynamic reference correction for fast and accurate load regulation

Low-dropout voltage regulators (LDOs) have been extensively used on-chip to supply voltage for various circuit blocks. Digital LDOs (DLDO) have recently attracted circuit designers for their low voltage operating capability and load current scalability. Existing DLDO techniques suffer from either poor transient performance due to slow digital control loop or poor DC load regulation due to low loop gain. A dual-loop architecture to improve the DC load regulation and transient performance is proposed in this work. The proposed regulator uses a fast control loop for improved transient response and an analog assisted dynamic reference correction loop for an improved DC load regulation. The design achieved a DC load regulation of 0.005mV/mA and a settling time of 139ns while regulating loads up to 200mA. The proposed DLDO is designed in 28nm FD-SOI technology with a 0.027mm2 active area.

A 0.5V supply, 49nW band-gap reference and crystal oscillator in 40nm CMOS

This paper presents the co-design of 0.5V operational band-gap reference (BGR) and 32kHz crystal oscillator (XO) in 40nm CMOS process. The proposed BJT-based BGR offers 10× resistor area reduction compared to the conventional BGR. The proposed XO provides trans-conductance enhancement without the need for large coupling capacitor and uses a feedback loop to regulate its bias current, oscillation amplitude across PVT. The total power consumption is less than 49nW from −40°C to 120°C. Without any trimming, the BGR achieves temperature coefficients of 8ppm/°C and XO has temperature coefficient of 0.25ppm/°C. The BGR offers 5× lower area, 2× lower power consumption at 120°C compared to prior work on resistor-based, non-duty cycled BGR. The XO improves power consumption by at least 2× compared to prior work at 120°C, 0.5V supply.

A 0.0175mm 2 600µW 32kHz input 307MHz output PLL with 190ps rms jitter in 28nm FD-SOI

A 32 kHz input analog phase-locked loop (PLL) is proposed which employs: (i) active capacitor multiplication technique for reducing PLL area wherein the input parasitic capacitance from the VCO is utilized for loop-filter capacitor realization, (ii) loop-filter noise reduction technique for lowering its noise contribution on integrated jitter at PLL output and (iii) charge-pump leakage reduction technique for improving reference-spur performance. Realized in 28nm UTBB FD-SOI process, the PLL outputs 307.2MHz clock, provides an integrated jitter of 190psrms, has reference spur of -59.5dB, occupies 0.0175mm2 area and consumes 600μW power. The PLL has an FOM of -196.6dB.

A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process

This paper presents a 32kHz input and 960MHz output low-power charge-pump phase-locked loop (CP-PLL) with a novel loop-filter resistor noise reduction technique and reverse sub-threshold leakage compensated source switched charge pump. The resistor noise reduction technique involves no additional active component / power overhead and hence, more beneficial than existing solutions. The PLL with minimum analog supply voltage of 1.62V and minimum digital supply voltage of 0.65V; with die area of 0.15mm2 is designed and fabricated in 28nm STMicroelectronics FDSOI process. The silicon measurement results have been included. Performance includes an integrated jitter of 530ps, reference spur of -65dBc and current consumption of 600μA.

Reflection of coupled generalized temperature rate dependent thermoelastic waves on a half space

A two-dimensional generalized thermoelastic model of the problem of reflection of P- and SV-waves on a half space of thermally conducting isotropic elastic material has been considered based on the Green–Lindsay theory. Ratios of reflection coefficients have been calculated for different cases and the results compared with the existing literature are presented in graphs.