Abhranil Maiti

A large scale characterization of RO-PUF

To validate the effectiveness of a Physical Unclonable Function (PUF), it needs to be characterized over a large population of chips. Though simulation methods can provide approximate results, an on-chip experiment produces more accurate result. In this paper, we characterize a PUF based on ring oscillator (RO) using a significantly large population of 125 FPGAs. We analyze the experimental data using a ring oscillator loop delay model, and quantify the quality factors of a PUF such as uniqueness and reliability. The RO-PUF shows an average inter-die Hamming distance of 47.31%, and an average intra-die Hamming distance of 0.86% at normal operating condition. Additionally, we intend to make this large RO frequency dataset available publicly for the research community.

Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators

A silicon Physical Unclonable Function (PUF), which is a die-unique challenge-response function, is an emerging hardware primitive for secure applications. It exploits manufacturing process variations in a die to generate unique signatures out of a chip. This enables chip authentication and cryptographic key generation. A Ring Oscillator (RO) based PUF is a promising solution for FPGA platforms. However, the quality factors of this PUF, which include uniqueness, reliability and attack resiliency, are negatively affected by environmental noise and systematic variations in the die. This paper proposes two methods to address these negative effects, and to achieve a higher reliability in an RO-based PUF. Both methods are empirically verified on a population of five FPGAs over varying environmental conditions, and demonstrate how practically useful RO-based PUF can be achieved.

Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive

In this paper, we analyze ring oscillator (RO) based physical unclonable function (PUF) on FPGAs. We show that the systematic process variation adversely affects the ability of the RO-PUF to generate unique chip-signatures, and propose a compensation method to mitigate it. Moreover, a configurable ring oscillator (CRO) technique is proposed to reduce noise in PUF responses. Our compensation method could improve the uniqueness of the PUF by an amount as high as 18%. The CRO technique could produce nearly 100% error-free PUF outputs over varying environmental conditions without post-processing while consuming minimum area.

A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions

We propose a systematic method to evaluate and compare the performance of physical unclonable functions (PUFs). The need for such a method is justified by the fact that various types of PUFs have been proposed so far. However, there is no common method that can fairly compare them in terms of their performance. We first propose three generic dimensions of PUF measurement. We then define several parameters to quantify the performance of a PUF along these dimensions. We also analyze existing parameters proposed by other researchers. Based on our analysis, we propose a compact set of parameters that will be used as a tool to evaluate as well as compare the performance of different PUFs. To make the method independent of the underlying PUF technique, we focus on the statistical properties of the binary PUF responses. We demonstrate the proposed method with a detailed comparison analysis between two PUFs: the ring-oscillator-based PUF (RO PUF) and the Arbiter-based PUF (APUF) using measured data from PUF implementations in state-of-the-art FPGAs. Finally, we present an online database where our measurements and analysis results can be consulted. Our dataset comprises measurements in 193 FPGAs.

A Robust Physical Unclonable Function With Enhanced Challenge-Response Set

A Physical Unclonable Function (PUF) is a promising solution to many security issues due its ability to generate a die unique identifier that can resist cloning attempts as well as physical tampering. However, the efficiency of a PUF depends on its implementation cost, its reliability, its resiliency to attacks, and the amount of entropy in it. PUF entropy is used to construct crypto graphic keys, chip identifiers, or challenge-response pairs (CRPs) in a chip authentication mechanism. The amount of entropy in a PUF is limited by the circuit resources available to build a PUF. As a result, generating longer keys or larger sets of CRPs may increase PUF circuit cost. We address this limitation in a PUF by proposing an identity-mapping function that expands the set of CRPs of a ring-oscillator PUF (RO-PUF) with low area cost. The CRPs generated through this function exhibit strong PUF qualities in terms of uniqueness and reliability. To introduce the identity-mapping function, we formulate a novel PUF system model that uncouples PUF measurement from PUF identifier formation. We show the enhanced CRP generation capability of the new function using a statistical hypothesis test. An implementation of our technique on a low-cost FPGA platform shows at least 2 times savings in area compared to the traditional RO-PUF. The proposed technique is validated using a population of 125 chips, and its reliability over varying environmental conditions is shown.

An analysis of delay based PUF implementations on FPGA

Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. Multiple delay based PUF architectures have been proposed. However, we have observed inconsistent results among them. Ring Oscillator PUF works fine, while other delay based PUFs show a significantly lower quality. Rather than proposing complex system level solutions, we focus on the fundamental building blocks of the PUF. In our effort to compare the various delay based PUF architectures, we have closely examined how each architecture maps into the FPGA fabric. Our conclusions are that arbiter and butterfly PUF architectures are ill suited for FPGAs, because delay skew due to routing asymmetry is over 10 times higher than the random variation due to manufacturing process.

Physical unclonable function and true random number generator: a compact and scalable implementation

Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signatures and volatile secret keys, whereas TRNGs are used for generating random padding bits, initialization vectors and nonces in cryptographic protocols. This paper proposes a scalable design technique to implement both a delay-based PUF and a jitter-based TRNG using ring oscillators. By sharing and reusing a significant amount of hardware resources, we achieve nearly 50% area reduction as compared to discrete implementations. We also propose and demonstrate a co-processor-based design that renders the circuit portable across various embedded processor platforms on FPGAs. Multiple scaled designs using 32 to 128 ring oscillators have been implemented and verified on Xilinx Spartan3S500E FPGA. A representative design uses 32 3-inverter ring oscillators, 64 flip-flops/latches, 31 2-input XOR gates and control circuitry giving a 3.2Mbps truly random stream and 31-bit unique device signature.

The Impact of Aging on an FPGA-Based Physical Unclonable Function

On-chip Physical Unclonable Functions (PUFs) are emerging as a powerful security primitive that can potentially solve several security problems. A PUF needs to be robust against reversible as well as irreversible temporal changes in circuits. While the effect of the reversible temporal changes on PUFs is well studied, it is equally important to analyze the effect of the irreversible temporal changes i.e. aging on PUFs. In this work, we perform an accelerated aging testing on an FPGA-based ring oscillator PUF (RO-PUF) and analyze how it affects the functionality of the PUF. Based on our experiment using a group of 90-nm Xilinx FPGAs, we observe that aging makes PUF responses unreliable. On the other hand, the randomness of PUF responses remains unaffected despite aging.

The Impact of Aging on a Physical Unclonable Function

On-chip physical unclonable functions (PUFs) have shown promises to solve several security problems. A PUFs behavior needs to be robust against reversible as well as irreversible temporal variabilities in circuits so that noise in the PUF output is minimized. While the effect of the reversible temporal variabilities on PUFs is well studied, sufficient attention has not been given so far to analyze the effect of the irreversible temporal variabilities i.e., aging on PUFs. In this paper, we perform an accelerated aging test on a ring oscillator (RO) PUF and analyze how it affects the functionality of the PUF. With our experiment using a set of 90-nm field-programmable gate arrays, we observe that aging makes PUF responses unreliable. Additionally, simulations show that the randomness of PUF responses remains unaffected despite aging. We also show that a passive countermeasure technique using a configurable RO can mitigate aging effect on the PUF significantly.

From Statistics to Circuits: Foundations for Future Physical Unclonable Functions

Identity is an essential ingredient in secure protocols. Indeed, if we can no longer distinguish Alice from Bob, there is no point in doing a key exchange or in verifying their signatures. A human Alice and a human Bob identify one another based on looks, voice, or gestures.