Leyla Nazhandali

A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency

A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and robust SRAM design enabled fully functional operation from 1.2V to 200mV. We analyze the variation in frequency and optimal voltage and evaluate the need for adaptive control. The processor reaches maximum energy efficiency at 360mV, consuming 2.6pJ/Inst at 833kHz. The minimum energy consumption of the core marks a 10times improvement over previous sensor processors at the same MIPS

Exploring Variability and Performance in a Sub-200-mV Processor

In this study, we explore the design of a subthreshold processor for use in ultra-low-energy sensor systems. We describe an 8-bit subthreshold processor that has been designed with energy efficiency as the primary constraint. The processor, which is functional below Vdd=200 mV, consumes only 3.5 pJ/inst at Vdd=350 mV and, under a reverse body bias, draws only 11 nW at Vdd=160 mV. Process and temperature variations in subthreshold circuits can cause dramatic fluctuations in performance and energy consumption and can lead to robustness problems. We investigate the use of body biasing to adapt to process and temperature variations. Test-chip measurements show that body biasing is particularly effective in subthreshold circuits and can eliminate performance variations with minimal energy penalties. Reduced performance is also problematic at low voltages, so we investigate global and local techniques for improving performance while maintaining energy efficiency.

Energy-Efficient Subthreshold Processor Design

Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point (Knin)- However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13-mum technology, which is sufficiently low to operate at Vmin . Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and Vmin across die to verify our analysis of adaptive tuning of the clock frequency and Vmin for optimal energy efficiency.

SenseBench: toward an accurate evaluation of sensor network processors

Sensor network processors introduce an unprecedented level of compact and portable computing. These small processing systems reside in the environment which they monitor, combining sensing, computation, storage, communication, and power supplies into small form factors. Sensor processors have a wide variety of applications in medical monitoring, environmental sensing, industrial inspection, and military surveillance. Despite efforts to design suitable processors for these systems (Ekanayake et al., 2004; Hempstead et al., 2005; Nazhandali et al., 2005; Wameke and Pister, 2004), there is no well-defined method to evaluate their performance and energy consumption. The historically used MIPS (millions of instructions per second) and EPI (energy per instruction) metrics cannot provide an accurate comparison because of their dependence on the nature of instructions, which differ across instruction set architectures. On the other hand, the current well-defined benchmarks (1989; Guthaus et al., 2001; Lee et al., 1997) do not represent typical workloads of sensor network systems, and hence, are not suitable to compare sensor processors. This paper defines a set of stream applications representing the typical real-time workload of a sensor processor. Furthermore, three new metrics, EPB (energy per bundle), xRT (times real-time), and CFP (composition foot print) are introduced to evaluate and compare such systems.

Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor

A robust, energy efficient subthreshold (sub-V_th) processor has been designed and tested in a 0.13 mum technology. The processor consumes 11 nW at V_dd = 160 mV and 3.5 pJ/inst at V_dd = 350 mV. Variability and performance optimization techniques are investigated for sub-V_th circuits.

A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution

In this paper we present a second-generation sensor network processor which consumes less than one picoJoule per instruction (typical processors use 100s to 1000s of picoJoules per instruction). As in our first-generation design effort, we strive to build microarchitectures that minimize area to reduce leakage, maximize transistor utility to reduce the energy-optimal voltage, and optimize CPI for efficient processing. The new design builds on our previous work to develop a low-power subthreshold-voltage sensor processor, this time improving the design by focusing on ISA, memory system design, and microarchitectural optimizations that reduce overall design size and improve energy-per-instruction. The new design employs 8-bit datapaths and an ultra-compact 12-bit wide RISC instruction set architecture, which enables high code density via micro-operations and flexible operand modes. The design also features a unique memory architecture with prefetch buffer and predecoded address bits, which permits both faster access to the memory and smaller instructions due to few address bits. To achieve efficient processing, the design incorporates branch speculation and out-of-order execution, but in a simplified form for reduced area and leakage-energy overheads. Using SPICE-level timing and power simulation, we find that these optimizations produce a number of Pareto-optimal designs with varied performance-energy tradeoffs. Our most efficient design is capable of running at 142 kHz (0.1 MIPS) while consuming only 600 fJ/instruction, allowing the processor to run continuously for 41 years on the energy stored in a miniature 1g lithium-ion battery. Work is ongoing to incorporate this design into an intra-ocular pressure sensor.

Circuit-level techniques for reliable Physically Uncloneable Functions

In this paper we study the effect of transistor supply voltage and body bias on the performance of ring oscillator Physically Uncloneable Functions (PUFs). The uniqueness (ability to identify a PUF) and reproducibility (ability to reproduce the same output) of PUFs increase drastically in the subthreshold region of operation. Also, the reproducibility of PUFs increase when the transistors are forward body biased. A ring oscillator PUF was tested and it achieved a uniqueness of 47.8% and reproducibility of 100% when operating at a supply voltage of 0.2 V. Compared to a base line configuration, our method improved the uniqueness by 18% and reproducibility by 7%. Therefore, apart from architectural optimizations, circuit level considerations like supply voltage and body bias can improve the reliability of PUFs.

Interlocking obfuscation for anti-tamper hardware

Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. Digital systems susceptible to tampering are of immense concern to defense organizations. First, offshore chip manufacturing allows the design secrets of the IP cores to be transparent to the foundry and other entities along the production chain. Second, small malicious modifications to the design may not be detectable after fabrication without anti-tamper mechanisms. Some techniques have been developed in the past to improve the defense against such attacks but they tend to fall prey to the increasing power of the attacker. We present a new way to protect against tampering by a clever obfuscation of the design, which can be unlocked with a specific, dynamic path traversal. Hence, the functional mode of the controller is hidden with the help of obfuscated states, and the functional mode is made operational only on the formation of a specific interlocked Code-Word during state transition. No comparator is needed as the obfuscation is embedded within the transition function of the state machine itself. A side benefit is that any small alteration will be magnified via the obfuscated design. In other words, an alteration to the design will manifest itself as a large difference in the circuits functionality. Experimental results on an Advanced Encryption Standard (AES) circuit from the open-source IP-cores suite suggest that the proposed method provides better active defense mechanisms against attacks with nominal (7.8%) area overhead.

Feedback Based Supply Voltage Control for Temperature Variation Tolerant PUFs

Physical Unclonable Functions (PUFs) are on-chip identifiers which have found many applications related to security. However, such devices suffer from instability due to time varying noise. Variation in operating temperature is a chief contributor to instability in PUFs. In this paper, we propose two different approaches to increase the stability of the popular ring oscillator PUFs against variations in temperature. The first approach involves using non-feedback based optimization of key circuit topologies including the drive strength of transistors and the stage length of the ring oscillators. However, to improve the stability even further, we propose a feedback based supply voltage control scheme. In this scheme, the supply voltage of the PUF is varied based on the operating temperature of the PUF IC. The optimal supply voltage to be applied to the PUF at each of the operating temperature is identified during the evaluation stage of the PUFs and is stored in the form of a micro-code. Also, a novel architecture supporting this scheme is proposed. Experimental results show that a 40% reduction in hardware is achieved by using this novel architecture.

From Statistics to Circuits: Foundations for Future Physical Unclonable Functions

Identity is an essential ingredient in secure protocols. Indeed, if we can no longer distinguish Alice from Bob, there is no point in doing a key exchange or in verifying their signatures. A human Alice and a human Bob identify one another based on looks, voice, or gestures.