Abir J. Mondal

Design of ultra low power flash ADC using TMCC & bit referenced encoder in 180nm technology

Analog-to-digital converters (ADCs) are needed in all those applications, which interface with the analogue world and exploit the digital processing of data. As digital processing is more and more gaining ground over analogue signal processing, the importance of ADCs correspondingly increases. The Flash type ADC, also known as Direct Conversion ADC, uses a bank of comparators, operating in parallel to achieve a high data conversion rate. In this paper, an area efficient low power high Speed 3-bit Flash Type ADC using bit referenced encoder is proposed in 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is also introduced as a modification of the conventional comparator. The proposed design of the ADC occupies an active area of 0.0036 mm2 and consumes 43.146 μW of average power while operating with an input frequency (fin) of 10 MHz and a supply voltage of 1.8 Volt.

FIR low pass filter design using Craziness base Particle Swarm Optimization Technique

This paper is a study of linear phase low pass FIR filter design using different particle swarm optimization techniques (PSO). FIR filter design is basically a multi-modal optimization problem. Evolutionary algorithms like particle swarm optimization (PSO) can be used for the design of linear phase FIR low pass (LP) filter. Different improved particle swarm optimizations are proposed to address different velocity vector and particle position updating scopes. The modified inertia weight of PSO enhances the search capability for obtaining the global optimal solution. The proposed modification is to monitor the linearly decreasing weights of particles. In this work we used Craziness based Particle Swarm Optimization algorithm (CRPSO) and checked the optimized output to make a comparative study of the conventional PSO techniques. The simulation result defines the optimization efficacy of the CRPSO algorithm for the solution of the non-linear, multimodal and non-differentiable FIR filter design problems.

A novel delay & Quantum Cost efficient reversible realization of 2 i × j Random Access Memory

As the conventional irreversible logic dissipates power for losing bits of information, computing engines has to be designed that do not require energy dissipation but only if computation is done logically reversible. Hence, research on reversible logic has been extensively increased now-a-days for its application in Quantum Computing, nanotechnology, QCA and Low power VLSI etc. In this paper, we have realized a Quantum Cost efficient Reversible RAM (RRAM) with a new 3×3 Reversible Gate named Modified Fredkin (MF). While approaching for RRAM we have also proposed a reversible D Flip-flop with minimum quantum cost (QC), a write enabled reversible master slave D Flip-flop & a (i × 2i) reversible decoder which has outperformed the existing designs in terms of quantum cost, ancilla & garbage outputs. We also have analyzed the architectures in terms of logical depth (worst case delay), hardly addressed in available literature.

Design of low noise high speed novel dynamic Analog Comparator in 65nm technology

Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the inputs is greater or lesser. Comparators, being an essential building block of most high speed devices like Analogue to Digital Converters, are one of the most important components used in signal processing and communication systems. Also it plays a challenging role in high speed mixed signal system designs. In this paper, we have presented an ultra-high speed simple dynamic comparator design using 65nm UMC technology. The circuit is operating at a clock frequency of 6.66GHz and input signal frequency of around 3.33GHz. The propagation delay is minimized to about 47.14ps with a low noise of about 0.531fV2/Hz which makes the proposed structure favourable for Flash or Pipelined data conversion applications. However, it uses only a total of 12 MOS transistors with minimum W/L ratios to make the circuit simple and area efficient, without affecting its performance. With the enhancement of speed and keeping other parameters like power & energy at its optimum value, this comparator circuit is a novel design that can be used in any high speed applications.

A CORDIC based design technique for efficient computation of DCT

A discrete cosine transform (DCT) is described and a technique to compute it using fast Fourier transform (FFT) is developed. In this work, DCT of a finite length sequence is obtained by incorporating CORDIC methodology in radix-2 FFT algorithm. The proposed methodology is simple to comprehend and maintains a regular structure, thereby reducing computational complexity. DCTs are used extensively in the area of digital processing for the purpose of pattern recognition. So the efficient computation of DCT maintaining a transparent design flow is highly solicited.

MOS Amplifier Design Methodology for Optimum Performance

While trying to represent the performance metrics of a single-stage amplifier as a function of designable parameters, it is observed that the corresponding metrics form a polytope-type feasible region. Indeed, the polytope so formed is made up of performance metrics which can either be objectives or constraints. Initially, the simplex method is used to obtain an objective value that satisfies a set of constraints. Once the objective is available, the interior point-based method is used to check whether any objective lies inside the feasible region or not. The proposed design flow examines both the periphery and the interior of the polytope so generated. Henceforth, the design of an amplifier can be pointed out to be a distinctive type of optimization concern, called Nonlinear Programming (NLP). Furthermore, efficient global optimization methods have been established to yield an automated synthesis of amplifiers derived from the requirements. In this work, the formulation of the design problem for a cascode amplifier as NLP is described and analyzed. Thereafter, the optimal trade-off curves related to the performance metrics such as small signal gain (Av), unity gain frequency (UGF) or gain bandwidth product (GBWP), and power are derived in order to observe the corresponding dependencies.

A constraint driven technique for MOS amplifier design

The performance of a single stage amplifier when expressed as a function of designable and technology related parameters can be improved by adjusting the component values and transistor dimensions. In the process to optimize the performance, the corresponding parameters can be expressed in terms of objective function and constraints so as to graphically form a polytope type feasible region. Thereafter, simplex method and interior point based method are used to find an optimal value by traversing through each of the corner point and interior of the polytope formed. Consequently, the amplifier design problem can be realized as a special form of optimization problem called Non Linear Programming (NLP), for which efficient global optimization methods have been developed. The present method yields completely an automated synthesis of single stage amplifiers directly from the specifications. In this paper, the proposed method is first described showing in detail the formulation of the design problem as NLP for a specific amplifier circuit and then applied to a wide variety of amplifier architectures. The optimal trade-off curves related to performance measures such as small signal gain(Av), unity gain frequency(UGF), slew rate(SR) and power are derived so as to observe the corresponding dependencies.

A method to design a comparator for sampled data processing applications

The performance of a comparator is significantly affected by the time taken to determine the unequal bit location so as to decide greater than, less than and equal to condition. Consequently, the delay will increase with the number of bits of a comparator. The reduction in delay so as to improve performance can be achieved with the introduction of multilevel look-ahead circuit. In this work, a unique architecture of comparator with look-ahead circuit is introduced to reduce the worst case delay and to improve the overall performance. First, a multilevel look-ahead circuit is described to reduce the critical path delay effectively. Secondly, the realization of the comparator and multilevel look-ahead circuit using domino logic significantly reduces the complexity of the entire architecture. At first, a 4-bit unit cell is designed using domino logic. Thereafter, an 8-bit macro is realized using the unit cell. Further, 16-bit, 32-bit and 64-bit circuits are developed using the proposed 8-bit macro and multilevel look-ahead circuit. Simulation results show that the proposed 64-bit circuit has improved power dissipation compared to existing architectures. Moreover, the worst case delay has reduced significantly and the entire operation can be performed in a single clock cycle.

Design and analysis of new energy efficient glitch free adiabatic logic circuit

The interest for ultra-low power integrated circuits in the recent past has guided the research community to establish the proposal of several adiabatic logic circuits in which the energy stored can be efficiently recycled. Many of these architectures suffer from problems like glitch & huge number of transistors as compared to conventional CMOS, which stop them to be used in practical scenario. As a consequence, we tried to come up with a new circuit that could address the above said limitations. In this work, we have proposed a new adiabatic logic where glitches are reduced drastically such that Logic 0 & Logic 1 level looks almost like what we generally have in conventional CMOS circuit output. The new logic is applied to design NOT, NAND & NOR gate as these are the fundamental building blocks of any digital system. The simulation of the circuits is done in 180 nm Technology and a significant savings in power and energy has been achieved after comparing with the conventional CMOS and a few previous well known adiabatic logics.

Amplifier design and optimization using Non Linear Programming

A generalized methodology to optimize the design of single stage amplifier is described. It is observed that a wide variety of constraints applied to the objective function graphically forms a polytope type feasible region. Simplex method and interior point based method are then used to find an optimal value by traversing through each of the corner point and interior, respectively, of the polytope formed. As a consequence, the amplifier design problem can be expressed as a special form of optimization problem called Non Linear Programming (NLP), for which efficient global optimization methods have been developed. Henceforth, we can efficiently determine tradeoffs between competitive performance measures such as small signal gain (Aυ), unity gain frequency (UGF), slew rate (SR) and power. In this paper, the proposed method is first described showing in detail the formulation of the design problem as NLP for a specific amplifier circuit and then applied to a wide variety of amplifier architectures. The proposed method yields completely an automated synthesis of single stage amplifiers directly from the specifications.