Alak Majumder

A novel realization of reversible LFSR for its application in cryptography

One-to-one mapping from input to output is the necessary condition for a reversible computational model transiting from one state of abstract machine to another. Probably, the biggest motivation to study reversible technologies is that, it is considered to be the best effective way to enhance the energy efficiency than the conventional models. The research on reversibility has shown greater impact to have enormous applications in emerging technologies such as Quantum Computing, QCA, Nanotechnology and Low Power VLSI. In this paper, we have realized novel reversible architecture of Linear Feedback Shift Register (LFSR) and Parallel Signature Analyzer (PSA) and have explored these in terms of delay, quantum cost and garbage. While approaching for LFSR, we have shown new reversible realization of Serial Input Serial Output (SISO) and Serial Input Parallel Output (SIPO) registers up to N-bit and analyzed their delay, quantum cost & garbage in terms of some lemmas, which will outperform the existing designs available in literature.

Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment

Advancement in payment technologies has an important impact on ones quality of life. Emerging payment technologies create both opportunities and challenges for the future. Being a quick and convenient process, contactless payment gained momentum, especially with merchants, with throughput being the main parameter. However, it poses risks to issuers, as no robust customer verification method is available. Thus, efforts have been underway to evolve and sustain a well-organized, efficient, reliable, and secure unified payment system, which may contribute to the smooth functioning of the market by eliminating obstacles in business.

Issues in NFC as a form of contactless communication: A comprehensive survey

Near Field Communication, being an emerging technology, has become an attractive area of research in academics as well as in industries due to its flooding growth and promising applications like short range contactless communication for mobile phone and other devices alike. In this regard, a proper understanding and direction of current research of NFC is to be perfectly maintained for the advancement of knowledge and to reduce the bridge gap between its basic theory and application practice. In this paper, we have proposed a thorough survey on NFC and discussed it in terms of our own visualization. We have found the problems available in the current technology of major industries like Apple, Google, Paypal and proposed some new thoughts to solve those. We also have analyzed the NFC business ecosystem and current / future market trends. In other words, this holistic review with the objective of bringing to state-of-the-art in NFC design provides development of knowledge in this field with future research directions.

Design of ultra low power flash ADC using TMCC & bit referenced encoder in 180nm technology

Analog-to-digital converters (ADCs) are needed in all those applications, which interface with the analogue world and exploit the digital processing of data. As digital processing is more and more gaining ground over analogue signal processing, the importance of ADCs correspondingly increases. The Flash type ADC, also known as Direct Conversion ADC, uses a bank of comparators, operating in parallel to achieve a high data conversion rate. In this paper, an area efficient low power high Speed 3-bit Flash Type ADC using bit referenced encoder is proposed in 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is also introduced as a modification of the conventional comparator. The proposed design of the ADC occupies an active area of 0.0036 mm2 and consumes 43.146 μW of average power while operating with an input frequency (fin) of 10 MHz and a supply voltage of 1.8 Volt.

A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to Ldi/dt. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1V for the device) gets changed, when various gates in a clock tree are turned ON at different times (Tn, parameters of the problem) with different values of current (In, other parameters of the problem). Basically, an ensemble of “n” number of transistors will be turned ON at time t=Tn while it will pump the total current I=In. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

A 90 nm leakage control transistor based clock gating for low power flip flop applications

The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information. The needless switching of clock, during the HOLD phase of either ‘logic 1’ or ‘logic 0’, may be abolished using gated clock. In this paper, we have presented a new clock gating technique incorporating Leakage Control Transistor. The improvised technique is employed to trigger a D-Flip Flop using 90nm PTM technology at 1.1V power supply. We have observed an impressive reduction in power, delay and latency using the proposed gating logic, which has outsmarted the existing works. The simulation is also performed in smaller technology nodes such as 65nm, 45nm and 32 nm to notice the change in delay, dynamic power and static power of the circuit.

Problems encountered in various arbitration techniques used in NOC router: A survey

As technology scales down toward deep submicron, large numbers of IP blocks are being integrated on the same Silicon die, thereby enabling large amount of parallel computations, such as those required for multimedia workloads. Network-on-chip (NOC) serves as an important agent to eliminate the communication bottleneck of future multicore systems. Arbiter, a prime component has a great impact on the feasibility of router. In this paper, we concentrate our ideas on the basic arbitration techniques with their features and found some problems with their roles in improving the performance of the routers and finally extending our range to a novel notion of overcoming extensive problems of starvation, HOL, congestion, etc. in a novel and feasible manners with a combination of the existing arbitration techniques in a more compact and sequential form.

FIR low pass filter design using Craziness base Particle Swarm Optimization Technique

This paper is a study of linear phase low pass FIR filter design using different particle swarm optimization techniques (PSO). FIR filter design is basically a multi-modal optimization problem. Evolutionary algorithms like particle swarm optimization (PSO) can be used for the design of linear phase FIR low pass (LP) filter. Different improved particle swarm optimizations are proposed to address different velocity vector and particle position updating scopes. The modified inertia weight of PSO enhances the search capability for obtaining the global optimal solution. The proposed modification is to monitor the linearly decreasing weights of particles. In this work we used Craziness based Particle Swarm Optimization algorithm (CRPSO) and checked the optimized output to make a comparative study of the conventional PSO techniques. The simulation result defines the optimization efficacy of the CRPSO algorithm for the solution of the non-linear, multimodal and non-differentiable FIR filter design problems.

A novel delay & Quantum Cost efficient reversible realization of 2 i × j Random Access Memory

As the conventional irreversible logic dissipates power for losing bits of information, computing engines has to be designed that do not require energy dissipation but only if computation is done logically reversible. Hence, research on reversible logic has been extensively increased now-a-days for its application in Quantum Computing, nanotechnology, QCA and Low power VLSI etc. In this paper, we have realized a Quantum Cost efficient Reversible RAM (RRAM) with a new 3×3 Reversible Gate named Modified Fredkin (MF). While approaching for RRAM we have also proposed a reversible D Flip-flop with minimum quantum cost (QC), a write enabled reversible master slave D Flip-flop & a (i × 2i) reversible decoder which has outperformed the existing designs in terms of quantum cost, ancilla & garbage outputs. We also have analyzed the architectures in terms of logical depth (worst case delay), hardly addressed in available literature.

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is ...