Abu Khari A'ain

CMOS Active Inductor Linearity Improvement Using Feed-Forward Current Source Technique

MOSFET drain current second-order nonlinearity has a significant impact on the linearity of current regulated CMOS active inductors. It tends to compress MOSFET transconductance (g m) by generating excess dc current (I EX) in the channel, which is a function of incoming input signal amplitude. This generated excess dc current can change the original dc operating point of the current regulated CMOS active inductor, and thus, influence the inductance. Unfortunately, MOSFET drain current second-order nonlinearity contributes more to MOSFET g m compression than MOSFET drain current third-order nonlinearity. In this paper, a new technique known as feed-forward current source (FFCS) has been proposed to improve the linearity of the active inductor. The proposed FFCS technique makes use of the second-order nonlinear property of a MOSFET that generates I EX when an input ac signal is applied. The generated I EX is then fed-forward to the current source of the active inductor to drain out the I EX in the active inductor. This prevents the dc operating point from shifting and improves its inductance linearity. Single-ended and differential active inductors with the proposed FFCS circuit have been fabricated using Silterras CMOS 0.18-mum technology to verify the proposed technique.

Design approach for tunable CMOS active inductor

A design approach for differential CMOS active inductor with a self-resonant frequency around 1.58GHz-3.98GHz is presented. The architecture is based on a differential gyrator-C topology to transform intrinsic capacitance of a MOSFET to the emulated inductance. Due to high power consumption of active inductor, only a current source is used. This design has the capability to tune the inductor and Q-factor values from 10nH-60nH and 20-60 respectively. Furthermore, a technique is proposed to ensure smaller inductance value can be achieved with smaller power consumption and die area.

A 2.4-GHz CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

A 2.4-GHz CMOS fully-integrated tunable image-rejection (IR) low-noise amplifier (LNA) has been designed using Silterras standard 0.18-mum CMOS process. The IR notch filter is designed using active inductor without using any passive inductor. With an image frequency of 1.34-GHz, post layout simulation results show the proposed IR LNA exhibits S21 of 27dB, S11 of -23.5dB, 2.2dB noise figure (NF) and input 1-dB compression point of -26dBm at 2.4-GHz. The IR of the IR LNA is -28dB and the tuning range for the IR notch filter is from 1.08 to 1.14-GHz. The first-stage of IR LNA dissipates not more than 10mw, including biasing circuit. The die area occupied by IR LNA is 0.49 mm 2, excluding GSG pads

Design of CMOS tunable image-rejection low-noise amplifier with active inductor

A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA) has been designed using Silterras industry standard 0.18 µm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA). A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of -17.8 dB, S22 of -10.7 dB, and input 1 dB compression point of -12 dBm at 3 GHz.

A 5 GHz CMOS Tunable Image-Rejection Low-Noise Amplifier

A 5 GHz image-rejection low-noise amplifier (IR-LNA) was designed using Silterras CMOS 0.18 mum RF process. The IR-LNA employs a tunable third-order notch filter to reject the image signal. The notch filter was designed using a metal-insulator-metal capacitor (MIM) and a high quality factor (Q) active resonator. The notch frequency of the filter can be tuned using active inductor. The IR-LNA was simulated using HSPICE with BSIM3v3 MOSFET models. Simulation results show that the IR-LNA exhibits S11 of -22.67 dB, S21 of 16.45 dB, S12 of -75.84 dB, 2.66 dB noise figure (NF), and -21.8 dBm input compression point (P1dB) at 5 GHz. The power dissipation of the IR-LNA is 15.46 mW. With an intermediate frequency of 550 MHz, the image-rejection of the notch filter is -16dB. The tuning range of the notch filter is from 3.30 GHz to 4.15 GHz with a maximum -36 dB image rejection

Adapting an on-line tutorial tool with web analytics to incorporate analysis of tutorial use

In this paper, consideration is given to extending an existing on-line tutorial system in order to understand the user experience with the tutorial by including analysis of the tool use. The areas of web analytics and learning analytics will be considered and used. Reference to how web analytics tools are used and the features they provide will be made. Features of available analytics tools will be considered and important features for use in an education context, and in particular this tutorial on-line tutorial system, will then be integrated into the tutorial for use by the tutorial administrator and developer.

The effects of gate oxide short in 6-transistors SRAM cell

The effects of gate oxide short (GOS) in a single 6-MOS transistors SRAM cell are studied in this work, through SPICE simulation. Both uni-directional split model and bi-dimensional lumped-transistors model are used to model the GOS in NMOS for comparison. It is assumed that only one NMOS is defective at a time. TSMC 0.18/spl mu/m process parameters are used in the SPICE simulations. Interesting findings and results showed that GOS may leave catastrophic impacts on SRAM operations.

A single-to-differential lna using differential active inductor for GPS applications

This paper presents the design of a single-ended input, differential output low noise amplifier for GPS applications in 0.18 μm CMOS technology. This Low Noise Amplifier (LNA) is composed of a common source (CS) amplifier adopted with a common gate, common source (CGCS) balun load. Instead of spiral on-chip inductor, a differential active inductor circuit (DAI) is used as an active load of balun and also gm-boosting technique is used to decrease the noise figure (NF) of Single-toDifferential Low Noise Amplifier (S-to-D LNA). The LNA is simulated with Cadence Spectra which shows the S21 of 22.94 dB at 1.57 GHz, S11 of −13.1 dB, NFmin of 2.66 dB and power dissipation of 2.5 mw from 1.8 V dc power supply. By adding an external capacitor to the DAI circuit, it is possible to reconfigure the LNA to use in multi frequency range. For using the LNA in frequency range of 1.22 GHz, the external capacitor is set to 121 fF. The result shows the S21 of 20.4 dB, S11 of −12.4 dB and NFmin of 2.4 dB.

Introductory laboratories in semiconductor devices using the Digilent Analog Discovery

In this paper, consideration is given to the use of the Digilent Analog Discovery in the teaching and learning of semiconductor devices and circuits. Specifically, an introduction to the characteristics and uses of diodes and transistors will be considered, along with the types of analogue and digital circuits that can be created using diodes and transistors. The features of the Analog Discovery will be considered and its use in the development of PC based experiments that can be performed away from a traditional laboratory by the student will be discussed. A case study circuit based on diode-transistor logic will be presented.

Internet based support tool for the teaching and learning of the IEEE standard 1500 for embedded core-based integrated circuits

In this paper, an education tool for assisting the teaching and learning of the IEEE 1500 standard testability method, used to support the testing of complex system-on-a-chip (SoC) integrated circuits (ICs), is developed and presented. The tool is an Internet browser based tool that supports the ability to investigate key aspects of the standard and its application to IC designs. The tool allows the user to create VHDL descriptions of both the test circuitry and the function circuitry via the Internet browser interface. The key considerations for developing this tool were to provide a computer based learning tool to support the teaching and learning of the standard and its application, and to allow the learner to investigate the design of integrated circuits that would require the use of this standard testability method through the use of VHDL (VHSIC hardware description language (HDL)).