Abusaleh M. Jabir

BCH code based multiple bit error correction in finite field multiplier circuits

This paper presents a design methodology for multiple bit error detection and correction in Galois field arithmetic circuits such as the bit parallel polynomial basis (PB) multipliers over GF(2m). These multipliers are crucial in most of the cryptographic hardware designs and hence it is essential to ensure that they are not vulnerable to security threats. Security threats arising from injected soft (transient) faults into a cryptographic circuit can expose the secret information, e.g. the secret key, to an attacker. To prevent such soft or transient fault related attacks, we consider fault tolerance as a method of mitigation. Most of the current fault tolerant schemes are only multiple bit error detectable but not multiple bit error correctable. Keeping this in view, we present a multiple bit error correction scheme based on the BCH codes, with an efficient bit-parallel Chien search module. This paper details the design procedure as well as the hardware implementation specs. Comparison with existing methods demonstrate improved area, and reduced delay performances.

Single error correctable bit parallel multipliers over GF(2 m )

Motivated by the problems associated with soft errors in digital circuits and fault-related attacks in cryptographic hardware, a systematic method for designing single error correcting multiplier circuits is presented for finite fields or Galois fields over GF(2 m ). Multiple parity predictions to correct single errors based on the Hamming principles are used. The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. This technique, when compared with existing ones, gives better performance. It is shown that single error correction (SEC) multipliers over GF(2 m ) require slightly over 100% extra hardware, whereas with the traditional SEC techniques, this figure is more than 200%. Since single bit internal faults can cause multiple faults in the outputs, this has also been addressed here by using multiple Hamming codes with optimised hardware.

On the design of different concurrent EDC schemes for S-Box and GF(p)

Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and reliable implementation of cryptographic algorithms in hardware must be able to detect or correct such malicious attacks. Error detection/correction (EDC), through fault tolerance, could be an effective way to mitigate such fault attacks in cryptographic hardware. To this end, we analyze the area, delay, and power overhead for designing the S-Box, which is one of the main complex blocks in the Advanced Encryption Standard (AES), with error detection and correction capability. We use multiple Parity Predictions (PPs), based on various error correcting codes, to detect and correct errors. Various coding techniques are presented, which include simple parity prediction, split parity codes, Hamming, Hsiao, and LDPC codes. The S-Box, GF(p), and PP circuits are synthesized from the specifications, while the decoding and correction circuits are combined to form the complete designs. The analysis shows a comparison of the different approaches characterized by their error detection capability.

MODD: a new decision diagram and representation for multiple output binary functions

This paper presents a new decision diagram (DD), called MODD, for multiple output binary and multiple-valued functions. This DD is canonic and can be made minimal with respect to a given variable order. Unlike other reported DDs, our approach can represent arbitrary combination of bits at the word-level. The preliminary results show that our representation can result in considerable memory saving.

GfXpress: A Technique for Synthesis and Optimization of

This paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m), where to is a nonzero positive integer. The technique is based on a graph-based decomposition and factorization of the polynomials, followed by efficient network factorization and optimization. A technique for efficiently computing the coefficients of the polynomials over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph-based representation. The technique has been applied to minimize multipliers over the fields GF(2k), where k = 2,...,8, generated with all the 51 primitive polynomials in the 0.18-mum CMOS technology with the help of the Synopsys design compiler. It has also been applied to minimize combinational exponentiation circuits, parallel integer adders and multipliers, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amounts. We also observed that the technique is capable of producing 100% testable circuits for stuck-at faults.

\hbox{GF}(2^{m})

This paper presents a design technique for multiple bit error correctable (fault tolerant) polynomial basis (PB) multipliers over GF(2^m). These multipliers are the building blocks in certain types of cryptographic hardware, e.g. the Elliptic Curve Crypto systems (ECC). One of the drawbacks in the existing techniques is their inability to correct multiple bit errors at the outputs. Also, much attention has been given to error detection, as opposed to error correction. However, owing to possible security threats induced by soft or transient faults in cryptographic hardware, in certain cases multiple bit error correction, as a way of mitigating attacks, is more important than detection. To this end, we use multiple parity predictions to detect multiple errors based on popular error correcting codes. First, we present a multiple error detection scheme using Low Density Parity Check Codes (LDPC). The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. For multiple bit error correction we use Reed Solomon codes. Comparison with traditional techniques shows improved area and power performance.

Polynomials

Motivated by the problems associated with soft errors in digital circuits and fault related attacks in cryptographic hardware, we presented a systematic method for designing single error correcting multiplier circuits for finite fields or Galois fields over GF(2m) in [7]. We used multiple parity predictions to correct single errors based on the Hamming principles. The problem with Hamming based error correction is the delay overhead. To mitigate the delay overhead, in this paper we present single error correction using Low Density Parity Check Codes (LDPC). The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. Our technique, when compared with existing techniques, gives better performance. We show that our Single Error Correction (SEC) multipliers over GF(2m) require slightly over 100 percent extra hardware, whereas with the traditional SEC techniques this figure is more than 200 percent.

Multiple Bit Error Detection and Correction in GF Arithmetic Circuits

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2m) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.

Fault tolerant bit parallel finite field multipliers using LDPC codes

This paper presents the generalized theory and an efficient graph-based technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. The technique presented for computing coefficients is unlike polynomial interpolation or matrix-based techniques and takes into consideration efficient graph-based forms which can be available as an existing resource during synthesis, verification, or simulation of digital systems. Techniques for optimization of the graph-based forms for representing the coefficients are also presented. The efficiency of the algorithm increases for larger fields. As a test case, the proposed technique has been applied to benchmark circuits over GF(2m). The experimental results show that the proposed technique can significantly speed up execution time.

C-testable bit parallel multipliers over GF (2 m )

This paper presents a new method for designing single error correcting Galois field multipliers over polynomial basis. The proposed method uses multiple parity prediction circuits to detect and correct logic errors and gives 100% fault coverage both in the functional unit and the parity prediction circuitry. Area, power and delay overhead for the proposed design technique is analyzed. It is found that compared to the traditional triple modular redundancy (TMR) techniques for single error correction the proposed technique is very cost efficient.