Adedotun Adeyemo

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays

In an effort to reduce the overall read/write power consumption in emerging memory technologies, efficient read/write schemes have recently attracted increased attention. Among these emerging technologies is the memristor-based resistive random access memory (ReRAM) with simpler structures and capability of producing highly dense memory through the sneak-path prone crossbar architecture. In this paper, a multiple-cells read solution to reduce the overall energy consumption when reading from a memory array is considered. A closed form expression for the noise margin effect is derived and analysis shows that there is zero sneak-path when sensing certain patterns of stored data. The multiple-cells readout method was thus used to analyse an energy efficient Inverted-Hamming (I-H) architecture capable of detecting and correcting single-bit write error in memristor-based memory array.

Novel memristive logic architectures

We present techniques for realising reliable logic functions and more complex systems based on the switching characteristics of memristors. First we show that memristors have inherent properties for representing multiple valued MIN-MAX logic over the post algebra. We also present efficient architectures for realising multifunction logic gates, and present a technique with hybrid 1T-4M architecture for seamless integration with existing CMOS logic. Memristors have tremendous potential for security aware hardware synthesis. To this end, we present design methods for realising highly efficient Galois Field circuits, which are widely used in crypto hardware, based on our 1T-4M architectures. Experimental results show that our proposed design requires significantly lower power while maintaining reliable operations at high frequencies compared to the CMOS counterparts.

Reliable gas sensing with memristive array

Gas sensing is one of the proposed application field of memristive devices. We used a crossbar array of memristors as gas sensor using the HP labs fabricated TiO2 based memristor model in an attempt to improve sensing accuracy. We introduced the possibility of reliable multiple gases detection using multiple rows of memristors as separate sensor in a crossbar array. Our experimental results show that an array of memristors can minimise measurement errors as well as provide a good redundancy measure during gas sensing. Measurements taken from the sensors are also not affected by alternate current paths problem often experienced in crossbar architecture.

Learning method for ex-situ training of memristor crossbar based multi-layer neural network

Memristor is being considered as a game changer for the realization of neuromorphic hardware systems due to its similarity with biological synapse. Recent studies show that memristor crossbar can provide high density and high performance neural network hardware implementation at low power due to its physical layout, nano scale size and low power consumption feature. This paper describes the training method that can be used for the implementation of memristive multi-layer neural network with ex-situ method. We mimic the behavior of memristor crossbar in software training process to achieve more accurate and close computations to hardware. Voltage divider has been used to calculate the dot product in this method. To demonstrate the accuracy and effectiveness of this method, different patterns and non-separable functions using memristor crossbar structures are simulated. The results demonstrate that more accurate computations can be produced using this learning method for ex-situ. It also reduces the learning time of functions.

Analytic models for crossbar read operation

Resistive memories have simpler structures and are capable of producing highly dense memory through crossbar architecture without the use of access devices. Reliability however remains a problem of resistive memories especially in its basic read operation. This paper presents a comprehensive model for resistive devices in crossbar array as well as models for four crossbar read schemes. These models are non-restrictive and are suitable for accurate analytical analysis of crossbar arrays and the evaluation of their performance during read operation.

Analytic models for crossbar write operation

This paper presents a circuit level analysis of write operation in memristor crossbar memory array with and without line resistance. Three write schemes: floating line, 1/2 and 1/3 are investigated. Analysis shows that floating line scheme could also be considered reliable in arrays with aspect ratio of 1:1 and negligible line resistance just like the latter two schemes. Further analysis also shows that high density crossbar structures cannot be designed using any of the three schemes with worst case line resistance and data distribution within the array. The presented analyses are suitable for modeling the crossbar array as well as evaluating performances during write operation. The output of this work provides the necessary design models that will assist designers in implementation of write techniques in crossbar array in future systems.

High level abstraction of memristor model for neural network simulation

Memristor emerged as an auspicious device in the field of neuromorphic engineering due to its nanoscale size, non-volatility, scalability, fast switching, low power consumption, high density and compatability with CMOS technology. This paper unveils the first mathematical memristor modeling in C ++. We also represent the implementation and training of a single layer and multilayer neural network using C++ memristor model. The memristive crossbar structure has been utilized to train the network. We successfully demonstrated linear and non-linear seperable logic functions using C++ memristor modeling in the simulation of neural network. We also demonstrated pattern classifier using single layer neural network at two different learning rates and the network performs satisfactorily at both the learning rates.

Write scheme for multiple Complementary Resistive Switch (CRS) cells

Amongst emerging technologies with the potential to usher in a new generation of Non Volatile Memory (NVM) is the memristor. The memristor makes it possible to build simple and highly dense memory structure via cross point architecture. Memristor array however suffers exponentially from sneak path leakages as array size increases, which leads to excessive power consumption and poor data integrity. Complementary Resistive Switch (CRS) was proposed to mitigate the sneak-path problem. However, when writing into multiple cells in CRS-based memory array, the state of unselected and and half-selected cell(s) in the array are affected in an undesired way depending on the polarity, magnitude and duration of the voltage applied during the write operation. The effect of these disturbance to non-selected cell(s) is a resultant corrupted output in subsequent read operation on these cell(s). In this paper, we reviewed the basic operation of the memristor and CRS cell in relation to their application as a memory device. Finally, we implemented an improved scheme for writing alternating data patterns into multiple cells in CRS-based memory array, we also examine how the initial state of the cell affects the performance of this scheme.