Adam C. Cabe

Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay

On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBTI PMOS current degradations across process, temperature, and varying activity factors. We show that a set of 1000 such small sensors can predict chip lifetime to an uncertainty of 7% to 10%. We also show that, once the total area dedicated to sensing is chosen, the lifetime prediction uncertainty is almost insensitive to the tradeoff between the number of sensors and the area of each individual sensor.

Designing CMOS/molecular memories while considering device parameter variations

In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.

SRAM-based NBTI/PBTI sensor system design

NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30× smaller than previous designs. Extensively reusing the SRAM peripheral circuitry minimizes control logic overhead. Sensing overhead is further amortized as the sensors can be both reconfigured and recycled as functional SRAM cells, potentially increasing SRAM yield when other bit cells fail due to initial process variation or long time aging effects. The paper also proposes a variation-aware sensor system design methodology by quantifying and leveraging the tradeoff between the size and number of sensors and the system sensing precision. Design examples show that a system of 500 sensors can achieve 4mV precision with 98.8% confidence, and a system of 1K sensors designed for 1M SRAM bit cells achieves 2000× area overhead reduction compared to a worst-case based approach.

Stacking SRAM banks for ultra low power standby mode operation

On-chip SRAM caches have come to dominate the total chip area and leakage power consumed in state-of-the-art microprocessor designs. Such large memories are necessary to attain high performance, however it is critical to minimize the idle currents drawn while these SRAM banks are inactive. This work proposes a novel voltage reduction technique to reduce SRAM leakage power during the standby mode. The design employs an implicit voltage reduction method that “stacks” SRAM banks in series while these blocks are inactive. No explicit DC/DC converters are required to achieve the reduced voltages, which leads to large area reductions over techniques requiring on-chip regulation circuits. This stacking technique reduces the voltage on each block close to the absolute data retention voltage (DRV) of each cell, and achieves a maximum leakage power reduction of 93% from the active power mode. Simulation results show the stability of the scheme around corners, process variations, and on-chip noise.

Tracking On-Chip Age Using Distributed, Embedded Sensors

Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging process provides one method to reduce large design margins that are otherwise required to offset circuit aging. This work extends previous research by contributing a sensing scheme that employs on-chip sensors capable of accurately tracking NBTI pMOS current degradations across process, temperature, and varying activity factors. Results show that a 7600 μm2 sensing area achieves an overall system accuracy of 90% at a voltage threshold precision of 2 mV. We thoroughly describe the sensor design and the underlying statistics used to determine overall accuracy and precision. Furthermore, a novel sensor distribution method is presented that uses an existing scan-chain methodology to mask the overhead of adding the on-chip sensors.

CORDIC implementation with parameterizable ASIC/SoC flow

A CORDIC processor with three computation modes is designed. The design targets low power applications. A novel fine grain clock gating scheme is employed to reduce power. The design is mapped to two technology nodes, i.e., 350 nm and 65 nm, using a script-based, parameterizable ASIC/SoC flow that can be easily adapted for different designs and technologies for fast concept-to-silicon mapping. Power numbers at both technology nodes are reported for the CORDIC design. The contribution of the paper includes both the actual design and the design flow.

Reducing stray currents in molecular memory through data encoding

Much progress is being made in the fabrication of molecular devices and nanoscale circuits. Such strides have led to studies and experimental tests using these devices in non-volatile memory arrays. However, the architecture of such arrays makes it difficult to accurately determine the value of each stored bit in the memory. When reading, each bit is effected by the rest of the memory through variable numbers of `stray current pathsiquest. This paper presents the idea of data encoding to thwart the impacts of these stray currents. The results show that this encoding method makes each bit unique and deterministic, independent of the memory array size. Details of the encoding scheme, the hardware design, and layouts are presented throughout this work.

Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM

Voltage stacking has been proposed as an efficient solution for power delivery in high performance processors, for 3D ICs, for pin-limited ICs, and for implicit sleep mode (standby) DC/DC conversion. In this paper we demonstrate voltage stacking for an 8Kb embedded SRAM in 180nm fully-depleted SOI (FDSOI) which leads to 88.6% reduction in standby power, including overhead. The SRAM is formed of two 4Kb subarrays which are powered in parallel during active mode, and stacked in series during standby. The SRAM uses no explicit decoupling or regulating and achieves active-to-sleep and sleep-to-active transitions of less than 10ns and a breakeven time of 20ns.

Teaching Top-Down ASIC/SoC Design vs Bottom-Up Custom VLSI

In the fast paced world of IC design, companies strive for ways to create competitive, robust designs, while delivering speedy time-to-market results. A top-down design flow provides a fast, results oriented design methodology, but, at most Universities, the strong legacy of the Mead/Conway approach has lead to custom methods being the default way to teach students VLSI design. This paper discusses some experiences with teaching a top-down System-on-a- Chip (SoC) design class.

A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors

Power and thermal considerations are becoming limiting factors for SoC designs as technology scales down. In this paper, a design methodology targeting a low-power and temperature-aware system is proposed. Dynamic voltage scaling (DVS) and dynamic thermal management (DTM) techniques are included. In order to demonstrate its effectiveness, we present an ongoing SoC design project of an ultrasound medical image processor incorporating a computationally intensive image enhancement algorithm. In particular, we show how DVS and DTM are adopted. A novel adaptive body-bias circuit that mitigates thermal sensitivity of circuits is also introduced.