Garrett S. Rose

Hardware realization of BSB recall function using memristor crossbar arrays

The Brain-State-in-a-Box (BSB) model is an auto-associative neural network that has been widely used in optical character recognition and image processing. Traditionally, the BSB model was realized at software level and carried out on high-performance computing clusters. To improve computation efficiency and reduce resources requirement, we propose a hardware realization by utilizing memristor crossbar arrays. In this work, we explore the potential of a memristor crossbar array as an auto-associative memory. More specificly, the recall function of a multi-answer character recognition based on BSB model was realized. The robustness of the proposed BSB circuit was analyzed and evaluated based on massive Monte-Carlo simulations, considering input defects, process variations, and electrical fluctuations. The physical constrains when implementing a neural network with memristor crossbar array have also been discussed. Our results show that the BSB circuit has a high tolerance to random noise. Comparably, the correlations between memristor arrays introduces directional noise and hence dominates the quality of circuits.

Memristor Crossbar-Based Neuromorphic Computing System: A Case Study

By mimicking the highly parallel biological systems, neuromorphic hardware provides the capability of information processing within a compact and energy-efficient platform. However, traditional Von Neumann architecture and the limited signal connections have severely constrained the scalability and performance of such hardware implementations. Recently, many research efforts have been investigated in utilizing the latest discovered memristors in neuromorphic systems due to the similarity of memristors to biological synapses. In this paper, we explore the potential of a memristor crossbar array that functions as an autoassociative memory and apply it to brain-state-in-a-box (BSB) neural networks. Especially, the recall and training functions of a multianswer character recognition process based on the BSB model are studied. The robustness of the BSB circuit is analyzed and evaluated based on extensive Monte Carlo simulations, considering input defects, process variations, and electrical fluctuations. The results show that the hardware-based training scheme proposed in the paper can alleviate and even cancel out the majority of the noise issue.

Fault Analysis-Based Logic Encryption

Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately

Leveraging Memristive Systems in the Construction of Digital Logic Circuits

4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.

Nano-PPUF: A Memristor-Based Security Primitive

The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal-oxide-semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.

An Energy-Efficient Memristive Threshold Logic Circuit

CMOS devices have been used to build hardware security primitives such as physical unclonable functions. Since MOS devices are relatively easy to model and simulate, CMOS-based security primitives are increasingly prone to modeling attacks. We propose memristor-based Public Physical Unclonable Functions (nano-PPUFs), they have complex models that are difficult to simulate. We leverage sneak path currents, process variations, and computationally intensive SPICE models as features to build the nano-PPUF. With just a few hundreds of memristors, we construct a time-bounded authentication protocol that will take several years for an attacker to compromise.

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory

Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.

A write-time based memristive PUF for hardware security applications

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.

Memristor based programmable threshold logic array

Hardware security has emerged as an important field of study aimed at mitigating issues such as piracy, counterfeiting, and side channel attacks. One popular solution for such hardware security attacks are physical unclonable functions (PUF) which provide a hardware specific unique signature or identification. The uniqueness of a PUF depends on intrinsic process variations within individual integrated circuits. As process variations become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies such as memristors become viable options for improved security in emerging integrated circuits. In this paper, we describe a novel memristive PUF (M-PUF) architecture that utilizes variations in the write-time of a memristor as an entropy source. The results presented show strong statistical performance for the M-PUF in terms of uniqueness, uniformity, and bit-aliasing. Additionally, nanoscale M-PUFs are shown to exhibit reduced area utilization as compared to CMOS counterparts.

Design Considerations for Multilevel CMOS/Nano Memristive Memory

In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.