Adam Norman

Electrical impact of high-speed bus crossing plane split

The importance of providing a continuous return current path for high-speed signal design is well recognized. A signal bus crossing a plane split has negative impact on SI (signal integrity) and EMI (electromagnetic interference). This paper provides numerical and/or measurement analysis to quantify these effects in the PCB environment, such as waveform distortion, increased crosstalk levels, and excessive radiation. In addition, simulation is used to quantify the effectiveness of mitigation techniques resulting in high-speed bus design guidelines.

Experimental and simulation analysis of single and differential signals changing layers

The physical effects surrounding the transition of a signal trace from one layer to another in a PCB design is studied both experimentally and numerically. This fundamental understanding is central to motherboard designs that are free from signal integrity and EMC/EMI deficiencies. The effects due to return current path discontinuities, current coupling, trace coupling and reference plane are considered. The results are interpreted from both a signal integrity (flight times and signal quality) and EMC/EMI standpoints. The findings will help drive better design practices into the PCB world.

Using Evolutionary Algorithms for Signal Integrity Checks of High-Speed Data Buses

Todays high performance computer systems must have fast, reliable access to memory and I/O devices. Unfortunately, inter-symbol interference, transmission line effects and other noise sources can distort data transfers. Engineers must therefore determine if bus designs have signal integrity .e., the bus can transfer data with minimal amplitude or timing distortion. One method of determining signal quality on buses is to conduct a set of data transfers and measure various signal parameters at the receiver end. But the tests must be conducted with stressful test patterns that maximize inter-symbol interference to help identify any potential problems. In this paper we describe how an evolutionary algorithm was used to evolve such test patterns. All test results were obtained intrinsically

A fast simulation method to measure the circuit nonlinearity

I/O circuits in high speed digital designs often exhibit strong nonlinearity, calling for efficient and effective characterizations. This paper presents a fast method to effectively measure the nonlinearity of the circuits. It provides a first quick assessment of the nonlinearity and helps to better guide the design to save design cost, time and reduce the complexity.

Using Evolutionary Algorithms for Signal Integrity Assessment of High-Speed Data Buses

Today’s high performance computer systems must have fast, reliable access to memory and I/O devices. Unfortunately, inter-symbol interference, transmission line effects and other noise sources can distort data transfers. Engineers must therefore determine if bus designs have signal integrity—i.e., can transfer data with minimal amplitude or timing distortion. One method of determining signal integrity on buses is to conduct a set of data transfers and measure various signal parameters at the receiver end. But the tests must be conducted with stressful test patterns that maximize noise to help identify any potential problems. In this paper we describe how an evolutionary algorithm was used to evolve test patterns for use in intrinsic testing.

Numerical conditional probability density function and its application in jitter analysis

Jitter is a critical factor to the performance of highspeed signal links. Jitter can be modeled as a random process. Both the probability density function (PDF) and the spectral characteristics of the jitter are important for evaluating the impact to the channel performance. The concept of numerical conditional probability density function (NCPDF) and a new statistical method called FastBER are proposed in this paper to accurately and efficiently perform the bit-error-rate (BER) analysis with taking into account both the PDF and the spectral characteristics of an arbitrary jitter sequence for arbitrarily low BER levels.

Wavelet compression for signal integrity analysis

Signal integrity (SI) analysis heavily relies on simulations. To support various interfaces and an increasing number of topologies, extensive simulations have been run over years. Such SI analysis is time and resource intensive, generating a huge amount of data. Can the existing big data set be exploited to ease our simulation and analysis efforts? In this work, we utilize wavelet techniques to compress one channel response (tens of thousands of data points) into only a small set of coefficients. There are many potential applications, if the reconstruction accuracy is maintained. One such application is to construct a Neural Net model of those coefficients over physical design parameters, such that the channel impulse response for any physical design can be obtained without any circuit simulation. This application, along with several others will be discussed in this paper. Moreover, wavelet-based techniques will be compared to more traditional compression techniques.

Method and applications of oscilloscope waveform de-embedding

At multi-Gbps data rates, the electrical impact of test and measurement structures can distort the intended signals to be measured. Many specifications, such as PCI-Express, define a compliance point at which the electrical performance of a component must be validated. To practically perform the measurement, test fixtures on the PCB and cables to measurement equipment are often a necessary part of the measurement setup. This paper discusses a methodology for de-embedding the effects of the text fixtures and cables to recover the time domain waveform at the compliance point. De-embedding formulations are given and validated by time-domain waveform simulations. The methodology is then applied to a practical design to solve a real-world problem.