Beomtaek Lee

A Flexible and efficient bit error rate simulation method for high-speed differential link analysis using time-domain interpolation and superposition

In this paper, a flexible and efficient time-domain method for calculating the bit error rate of high-speed differential links is presented. The method applies interpolation and superposition to the step response of a channel to construct the jittery data or/and clock waveforms at the receiver. With the statistics of the actual reference-crossing points extracted from the constructed receiver waveforms, the bathtub curves can be derived and extrapolated to get the eye margin at the given bit error rate. A software has been developed and applied for high-speed differential link design using the method. Good correlation has been achieved between the simulated results using this method and the measurement data with a bit error rate tester.

A 400-MT/s 6.4-GB/s multiprocessor bus interface

This paper describes the design of a system bus interface for the 130-nm Itanium/sup /spl reg//2 processor that operates at 400MT/s (1 megatransfer = 1 Mb/s/pin) with a peak bandwidth of 6.4 GB/s. The high-speed operation is achieved by employing source-synchronous transfer with differential strobes. Short flight time is accomplished by double-sided placement of the processors. Preboost and postboost edge-rate control enables fast clock-to-output timing with tight edge-rate range. The built-in input/output (I/O) loopback test feature enables I/O parameters to be tested on die, using a delay-locked loop and interpolator with 21-ps phase-skew error and 15-ps rms jitter. Power modeling methodology facilitates accurate prediction of system performance.

High speed differential I/O overview and design challenges on Intel enterprise server platforms

In this paper, the high speed differential I/O buses which are used on Intel server platforms are explored. The characteristics of channel components are examined along with channel and I/O circuit design challenges. Statistical time domain and frequency domain methods are briefly discussed as start-of-art simulation tools.

A 400MT/s 6.4GB/s multiprocessor bus interface

A 0.13/spl mu/m 1.2V GTL bus interface with compensated slew rate and termination achieves 400MT/s at a 6.4GB/s data rate in a 5-load MP environment. Packaged on an FCBGA and interposer with 5:1:4 signal to power and ground ratio and routed on 12mm 45/spl Omega/ traces, the interface incorporates I/O timing self test supported by a DLL and an interpolator with 25ps peak-to-peak jitter.

Suppression of Cavity Resonant Edge Effects and PDN impedance using absorbing material

Cavity Resonant Edge Effects (CREE) in printed circuit boards (PCBs) and packages can cause severe power integrity (PI) and electromagnetic interference/compatibility (EMI/EMC) issues. Electromagnetic radiation from PCB edges are major sources of EMI/EMC problems in electronic devices. Power supply noise, in the form of fast changing currents (di/dt), traverses the power-return paths of PCBs and packages using power vias. CREE produces considerable level of noise along the edges of PCB and package power planes due to signal coupling between vias and reflection along PCB edges with transient currents. In this paper, we investigate an approach to minimize cavity resonant noise by placing absorbing material along the edges of a PCB board. The upper peak (anti-resonant) impedance of the power distribution network (PDN) is reduced significantly. In this paper the simulated example shows the absorbing material reduces the upper impedance peaks as much as to 8% comparing to the impedance peaks without absorption material. Conclusively, the results show that adding absorbing material along the PCB edges significantly improves the noise issues by suppressing CREE.

Suppression of Couplings in High-Speed Interconnects Using Absorbing Materials

In this paper, we propose and investigate two novel applications of absorbing materials to suppress high-frequency couplings in high-speed interconnects. In the first application, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances. In the second application, a low-emission inductor is proposed by applying absorbing materials surrounding the body of an inductor. Full-wave simulations and measurements are performed to verify the proposed techniques. Results show absorbing materials significantly improve the performance of signal/power integrity and greatly reduce electromagnetic interference for high-speed digital system designs.

Stub Effect Mitigations Using Absorbing Materials

A new technology is developed for the mitigation of stub effects in high-speed interconnects. This technology substantially reduces the stub effects for high-speed signaling. It dampens reflected signals on stubs, thus reducing intersymbol interference and harmful coupling, and correcting timing jitter, all typically induced by the stubs reflected signals. This paper shows two applications for high-speed digital system designs, the mitigation of via stub effects and that of empty connector effects, respectively. However, it is notable that the present method is suitable for reflection suppression for arbitrary types of stubs to improve the signal integrity.

Rigorous one-port measurement method for the characterization of on-chip pad response

The paper presents a rigorous, one-port measurement technique for the characterization of on-chip pad response, particularly the pad capacitance (Cpad). By adding two independent (“short” and “match”, or two terminations with known impedance other than “open”) standards to the existing one-port method, the method eliminates the errors in the current vector network analyzer (VNA) method, while providing frequency-dependent data. This not only overcomes the fundamental restriction in conventional two-port measurement methods that are prohibitively complex, but also is better than existing one-port methods that are inaccurate due to lack of two independent measurements. Simulations and experiments are performed to validate the proposed method in the paper.

Differential symmetry principle for differential crosstalk cancellation

The paper introduces the usage of the differential symmetry principle to minimize or even cancel differential crosstalk. Applications to a CPU socket with hexagonal pin map pattern and to an edge connector are described. It is shown how a careful consideration of pin location and differential pair orientation can result in a high signal density and low differential crosstalk design.

Novel de-embedding method with Look-Up Table for characterization of interconnects

A new de-embedding technique is introduced in this paper with pre-established Look-Up Table (LUT) for accurate characterization of high speed interconnects, particularly for printed circuit board (PCB). The method de-embeds the test fixture effects from the measurement or/and simulation results. It improves the accuracy and reduces the PCB layout area comparing to one line method. It reduces the PCB layout area and improves the measurement efficiency comparing to two line method.