Adán Kohler

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.

Fault-tolerant architecture and deflection routing for degradable NoC switches

Networks-on-Chips (NoCs) provide inherent structural redundancy of on-chip communication pathways. This redundancy can be exploited to maintain connectivity even if some components of an NoC exhibit faults which will appear at an increasing rate in future chip generations. Based on a fine-grained functional fault model, error-detecting circuitry, and distributed online fault diagnosis, we determine the fault status of NoC switches, including their adjacent links. The remaining functionality of partly defective switches is utilized by a modified deflection routing algorithm to achieve graceful degradation of packet throughput.

Low-Latency Collectives for the Intel SCC

Message passing has been adopted as the main programming paradigm for many-core processors with on-chip networks for inter-core communication. To this end, message-passing libraries such as MPI can be used, as they provide well-known interfaces to application developers. Since MPI implementations were originally developed for macroscopic computer networks, the different characteristics of on-chip networks may require rethinking existing solutions. With the example of All reduce, we identify points where collective operations benefit from routines optimized for on-chip networks. The identified issues are then applied to additional collectives including Broadcast, All gather and All to all. The effectiveness of the proposed optimizations is demonstrated on the Single-Chip Cloud Computer (SCC), a many-core research chip created by Intel Labs. Experiments show that collective operations subjected to the identified optimizations are accelerated by factors roughly between 2 to 3 compared to current state of the art implementations. In addition to synthetic benchmarks, we show that the use of the optimized routines accelerates a scientific application by more than 40%.

Optimized Reduce for Mesh-Based NoC Multiprocessors

Future processors are expected to be made up of a large number of computation cores interconnected by fast on-chip networks (Network-on-Chip, NoC). Such distributed structures motivate the use of message passing programming models similar to MPI. Since the properties of these networks, like e.g. the topology, are known and fixed after production, this knowledge can be used to optimize the communication stack. We describe two schemes that take advantage of this to accelerate the (All-)Reduce operation defined in MPI, namely a contention avoiding rank-to-core mapping and a way of interleaving communication and computation by means of pipelining. Simulations show that the combination of both schemes can accelerate (All-)Reduce operations by more than 60%.

Degradability Enabled Routing for Network-on-Chip Switches

Abstract Network-on-Chip topologies provide inherent redundancy of communication paths between sources and sinks. By disabling faulty parts and choosing alternative routes, this redundancy can be exploited for preventing packets from being corrupted. In this article we present a formalized and generalized description of adaptive routing algorithms that allow utilizing the remaining functionality of partly defective switches. An example shows that, compared to taking such defective switches offline, a more graceful degradation of communication performance is achieved. Zusammenfassung Network-on-Chip-Topologien weisen redundante Kommunikationspfade zwischen Quellen und Senken auf. Dies erlaubt es, von Fehlern betroffene Teile zur Vermeidung von Paketverlusten zu deaktivieren und durch Wahl alternativer Routen zu umgehen. In diesem Artikel beschreiben wir formal und verallgemeinert die Anpassung von Routingverfahren zur weitestgehenden Nutzung noch bestehender Restfunktionalität von teildefekten Switches. Ein Beispiel zeigt, dass damit ein im Vergleich zur vollständigen Abschaltung fehlerbehafteter Switches nur graduelles Absinken der Kommunikationsleistung erzielt wird.

Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors

Since the end of the Megahertz Race, the main factor in improving processor performance has been the increase of the number of cores integrated on a single chip. While four-, six- and eight-core processors are standard today, future designs with even higher core counts encounter scalability problems concerning the on-chip interconnect and power dissipation. For the interconnect problem, regular tile-based designs that employ a Network-on-Chip to provide inter-core connectivity have been proposed as solution. To mitigate the power consumption issue, we present a system for exploiting idle time in high-performance applications by reducing a cores frequency, thus saving power without affecting performance. The system relies on annotation of synchronizing communication calls and has been shown to reduce the energy requirements of considered applications by 20-30%, while introducing negligible overhead in terms of runtime.

Cost-Based Deflection Routing for Intelligent NoC Switches

Future manycore systems-on-chip will employ packet-switched, multi-hop interconnection networks-on-chip (NoC). In order to cope with disturbances from, e.g., faults or local traffic overload, some degree of intelligence and adaptivity has to be built into NoC switches. They need to know about their own and their environment’s fault and traffic status and take this information into account when making routing decisions. We present an approach that selects optimized routes based on a routing cost function which includes route length, fault status, and traffic congestion all at the same time. We present an efficient implementation of cost based deflection routing and investigate its communication performance.