Gert Schley

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.

Optimal placement of vertical connections in 3D Network-on-Chip

Due to technological limitations, manufacturing yield of vertical connections (Through Silicon Vias, TSVs) in 3D Networks-on-Chip (NoC) decreases rapidly when the number of TSVs grows. The adoption of 3D NoC design depends on the performance and manufacturing cost of the chip. This article presents methods for allocating and placing a minimal number of vertical links and the corresponding vertical routers to achieve specified performance goals. A second optimization step allows to maximize redundancy in order to deal with failing TSVs. Globally optimal solutions are determined for the first time for meshes up to 17x17 nodes in size. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, an optimal placement with 25% of vertical connections achieved 81.3% of average network latency and 76.5% of energy delay product, compared with full layer-layer connection. The performance with 12.5% and 6.25% of vertical connections are also evaluated. Our analysis and experiment results provide a guideline for future 3D NoC design.

On Covering Structural Defects in NoCs by Functional Tests

Structural tests provide high defect coverage by considering the low-level circuit details. Functional test provides a faster test with reduced test patterns and does not imply additional hardware overhead. However, it lacks a quantitative measure of structural fault coverage. This paper fills this gap by presenting a satisfiability based method to generate functional test patterns while considering structural faults. The method targets NoC switches and links, and it is independent of the switch structure and the network topology. It can be applied for any structural fault type as it relies on a generalized structural fault model.

Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip

A reliable data exchange between cores of a Network-on-Chip (NoC) is of great importance for correct system behavior. However, data exchange is aggravated by the occurrence of transient and permanent faults in the NoCs communication structure (links). These faults may cause corruption or loss of data which in turn may lead to performance degradation or, in worst case, to complete system failure. In case data is corrupted by a transient fault, a common measure to handle this is to retransmit the data. To ensure that faulty data is retransmitted, so called flow control protocols are applied. In case of permanent faults a simple retransmission is not possible. Permanent faults in e.g. links lead to a permanent corruption of data as long as they are not located. Thus, even retransmissions get corrupted. In this paper we present a fault tolerant end-to-end protocol applicable to arbitrary NoC topologies. It ensures reliable end-to-end communication in presence of transient and permanent faults in the interconnection structure. By means of the protocols online diagnostic ability, it is capable of locating faulty links and switches without any additional diagnosis hardware.

Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds

This article presents our experience in design of a practical syllabus part of a graduate level embedded systems engineering program for students with multidisciplinary backgrounds. The aim of this syllabus is to address practical issues in design and development of embedded systems composed of software and hardware. It is implemented in a full-semester lab project and a series of practical exercises accompanying the Embedded Systems Engineering Lecture course offered by our group, and complements its theoretical foundations. The syllabus described in this paper was first devised in summer term 2007 and has been improved in winter term 2010/11. The presented syllabus together with the corresponding lab infrastructure allows incorporation of diverse embedded system architectures in future.

Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy

Adding logical hierarchy to networks-on-chip enables table-based routing without excessive chip area overhead. For a 256 node network, the routing table occupies only less than 20% of the switches area. Thanks to the hierarchical network organization, double data throughput is achieved, compared to a flat network of same size.Table-based routing can be used to implement fault-tolerant routing by reconfiguring table entries. The article shows how table entries can be computed efficiently, and how the reconfiguration process can be organized to function reliably even in presence of transmission errors.With proper choice of logical hierarchy, the reconfiguration process takes less than one third of the time required by Ariadne, the state-of-the-art approach for non-hierarchical networks.The additional hardware overhead for fault-tolerant routing table reconfiguration amounts to only 6% of the chip area of a network switch. This paper presents a reconfigurable fault tolerant routing for Networks-on-Chip organized into hierarchical units. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16 × 16 network show a speedup by a factor of almost four for routing reconfiguration compared to the state-of-the-art approach. Evaluation with transient faults shows that a dedicated reconfiguration unit enables successful reconfiguration of routing tables even in case of high error probabilities.

Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip

With increasing number of processing elements on a single chip, the size of the Network-on-Chip connecting the processing elements increases accordingly. This leads to new challenges for components such as fault diagnosis and routing because they do not scale with the size of the Network-on-Chip, e.g. regarding the required communication overhead or their implementation costs. A measure to avoid these scaling problems is to organize future Networks-on-Chip hierarchically. This paper presents a fault tolerant routing for Networks-on-Chip organized into hierarchical units where each unit manages its own routing. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16x16 network show a speedup of three for routing reconfiguration compared to state-of-the-art approach. At the same time our approach achieves a memory reduction for routing tables by a factor of seven compared to flat network tables.

Degradability Enabled Routing for Network-on-Chip Switches

Abstract Network-on-Chip topologies provide inherent redundancy of communication paths between sources and sinks. By disabling faulty parts and choosing alternative routes, this redundancy can be exploited for preventing packets from being corrupted. In this article we present a formalized and generalized description of adaptive routing algorithms that allow utilizing the remaining functionality of partly defective switches. An example shows that, compared to taking such defective switches offline, a more graceful degradation of communication performance is achieved. Zusammenfassung Network-on-Chip-Topologien weisen redundante Kommunikationspfade zwischen Quellen und Senken auf. Dies erlaubt es, von Fehlern betroffene Teile zur Vermeidung von Paketverlusten zu deaktivieren und durch Wahl alternativer Routen zu umgehen. In diesem Artikel beschreiben wir formal und verallgemeinert die Anpassung von Routingverfahren zur weitestgehenden Nutzung noch bestehender Restfunktionalität von teildefekten Switches. Ein Beispiel zeigt, dass damit ein im Vergleich zur vollständigen Abschaltung fehlerbehafteter Switches nur graduelles Absinken der Kommunikationsleistung erzielt wird.

Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip

In order to tolerate faults that emerge in operating Networks-on-Chip, diagnosis techniques are employed for fault detection and localization. On various network layers, diverse diagnosis methods can be employed which differ in terms of their impact on network performance (e.g., by operating concurrently versus pre-empting regular network operation) and the quality of diagnostic results. In this contribution, we show how diagnosis techniques of different network layers of a Network-on-Chip can be combined into multi-layer solutions. We present the cross-layer information flow used for the interaction between the layers and show the resulting benefit of the combination compared to layer-specific diagnosis. For evaluation, we investigate the diagnosis quality and the impact on system performance to explore the entire design space of layer-specific techniques and their multi-layer combinations. We identify pareto-optimal combinations that offer an increase of system performance by a factor of four compared to the single-layer diagnosis.