Adewale Adetomi

A dynamic partial reconfiguration design for camera systems

The image-processing pipeline is the core part of any camera system including digital still cameras, camcorders, camera phones and video surveillance equipments. The image-processing pipeline consists of a number of processing stages that enhance the image or remove any effects that are caused by surrounding conditions. These stages are computationally intensive and need special requirements to meet the real time processing. This paper discusses the pipeline parts and presents a high-performance and cost-effective implementation of the pipeline on Field Programmable Gate Arrays (FPGAs) using Dynamic Partial Reconfiguration (DPR) feature to exploit the FPGA resources over time and space. The paper shows that the implemented system adds much of flexibility to camera systems by using a reconfigurable region. The system can use an unlimited number of image processing pipeline stages to process the images without the need of huge number of logic resources to fit all the stages. Moreover, the stages are not fixed in this system, they can be changed upon the users decision. The architecture is designed to process still images of size 1920×1080. Each stage could process a full frame within 7.25 ms. A fast configuration engine is designed and deployed in the system. The engine shows that it can outperform the engine provided with zynq SoC by three times. The overall throughput of the system reaches 250 Megapixel/s.

Clock Buffers, Nets, and Trees for On-Chip Communication: A Novel Network Access Technique in FPGAs

The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present CELOC, a Clock-Enabled Low-Overhead Communication technique. It is a network access technique that uses the clock buffers of an FPGA as serial communication links in order to reduce the overhead contributed by the NoC links. This technique involves toggling the clock enables of clock buffers to transmit communication signals from one circuit to another. A demonstrator based on a Xilinx 7 series FPGA showed that a single link can achieve a bandwidth of 6.5 Gbps at 100 MHz.

FAReP: Fragmentation-Aware Replacement Policy for Task Reuse on Reconfigurable FPGAs

The use of reconfigurable chips such as FPGAs in embedded systems for many runtime applications is limited by large reconfiguration time. Techniques to circumvent this limitation relies on hardware task reuse which preserve certain circuits on the chip. However, the frequent addition and removal of circuits while preserving others on the chip will inevitably lead to fragmentation of its area, in an ongoing manner. In this paper, we present a fragmentation-aware replacement policy (FAReP) for reusing tasks on reconfigurable chips. FAReP aims not only at circumventing reconfiguration time, but also offering some defragmentation of the chip area at no extra reconfiguration cost. Our results show that FAReP leads to a reduced task rejection ratio, at least a 13% reduction in average unused chip area and up to 29% of reconfiguration time could be avoided compared to state of the art techniques based on task reuse.

Relocating Encrypted Partial Bitstreams by Advance Task Address Loading

The ability to relocate hardware tasks in FPGAs is an attractive task management technique, especially in reconfigurable operating systems. A method of relocation involves the modification of the location address of the task while it is being configured. However, the use of encryption to protect bitstreams requires that decryption is done on-chip before relocation. This usually results in a significant resource overhead, arising from the introduced decryption circuit. This paper presents Advance Task Address Loading (ATAL), a unique solution that involves loading the unencrypted task address ahead of the encrypted tasks configuration frame data. We have developed a software named Splixbit, which processes the bitstream offline, and a corresponding hardware configuration controller that configures the bitstream on the FPGA. Our results confirmed the possibility of avoiding on-chip dedicated decryption circuit in relocating encrypted partial bitstreams.

A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs

Runtime relocation of circuits on field-programmable gate arrays (FPGAs) has been proposed for achieving many desirable features including fault tolerance, defragmentation, and system load balancing. However, the changes in the architectural composition of FPGAs have made relocation more challenging mainly because FPGAs have become more heterogeneous. Previous and state-of-the-art circuit relocation systems on FPGAs have relied only on direct bitstream relocation which requires the source and destination resource layouts to be the same, as well as access to the design bitstream for manipulation. Hence, their efficiency on modern heterogeneous chips greatly reduces, and mostly cannot be applied to encrypted bitstreams of intellectual property blocks. In this brief, we present a circuit relocator which augments direct bitstream relocation with a functionality-based relocation scheme. We demonstrate the feasibility of the proposed technique using a CORDIC application and show that an average of over 2.6-fold increase in the number of relocations can be obtained compared to only direct bitstream relocation at the expense of a small memory overhead and manageable relocation time for this case study.

A placement management circuit for efficient realtime hardware reuse on FPGAs targeting reliable autonomous systems

Reconfigurable hardware such as FPGAs offer promising platform for the development of embedded autonomous systems. This is due to their unique combination of high performance and flexibility. However, state-of-the-art FPGAs have large reconfiguration time, which often leads to missed deadlines in real-time systems. They also suffer from considerable fragmentation during runtime placement, leading to poor chip area utilization. In this paper, we present a novel hardware-placement management circuit to address these limitations by offering circuit reuse and a low-cost defragmentation. Its implementation occupies only 1852 FPGA slices. Our results showed that over 70% of configuration time was circumvented compared to state-of-the-art techniques. In addition, up to 56% improvement in reuse efficiency was observed.

Towards an efficient intellectual property protection in dynamically reconfigurable FPGAs

The trend in computing is towards the use of FPGAs to improve performance at reduced costs. An indication of this is the adoption of FPGAs for data centre and server application acceleration by notable technological giants like Microsoft, Amazon, and Baidu. The continued protection of Intellectual Properties (IPs) on the FPGA has thus become both more important and challenging. To facilitate IP security, FPGA vendors have provided bitstream authentication and encryption. However, advancements in FPGA programming technology have engendered a bitstream manipulation technique like partial bitstream relocation (PBR), which is promising in terms of reducing bitstream storage cost and facilitating adaptability. Meanwhile, encrypted bitstreams are not amenable to PBR. In this paper, we present three methods for performing encrypted PBR with varying overheads of resources and time. These methods ensure that PBR can be applied to bitstreams without losing the protection of IPs.

Relocation-aware communication network for circuits on Xilinx FPGAs

The parallelism of hardware and the dynamic reconfigurability of FPGAs enable multiple hardware tasks to run concurrently, and also time-share resources by being swapped in and out of the device during runtime. More than ever before, these capabilities are being employed in systems with high-reliability requirements. To improve reliability, a method often used is circuit relocation. However, the static nature of conventional FPGA communication interconnects is a bane to flexible runtime relocation. This paper employs a novel network architecture to enable dynamic communication and thus improve the flexibility of circuit relocation. By using the clock infrastructure of the FPGA as the physical network links for tasks in a 4-node star network, we have shown that dynamic communication between relocatable circuits can be achieved without incurring any overheads of time and resources, save for only 32 slices used for the Network Interface.

Expanding the un-usable area strategy for improved utilization of reconfigurable FPGAs

The addition of hard blocks such as Block RAMs and Digital Signal Processors, have proven to be good means of improving various performance metrics in FPGAs. This however places stricter constraints on runtime relocation of hardware tasks and hence reduces their application in dealing with permanent faults. In this paper, we present a strategy that enhances the utilization of heterogeneous reconfigurable FPGAs by minimizing resources which are tied down as unusable areas. Our results show that the strategy leads to a 9.4% reduction in task rejections and improved placement quality compared to state of the art techniques. The complete implementation occupies only 1712 LUTs and 1645 Flip Flops on the Xilinxs xc7z100ffg900-2. Based on this strategy, more task relocations can be obtained which enhances the capacity of FPGAs to deal with permanent faults.

A fault-tolerant ICAP controller with a selective-area soft error mitigation engine

Dynamic partial reconfiguration (DPR) allows runtime access to the configuration memory (CMEM) of FPGAs. A key function that relies on DPR is task reconfiguration, where circuits are multiplexed in time and space in order to reduce device count and cost. Moreover, in mission-critical applications, DPR is used for soft error mitigation (SEM). These two key functions require access to the same CMEM interface and the recommendation is that more time (> 99%) should be allocated to SEM for continuous full-device reliability. We present a fault-tolerant controller with a fully integrated SEM engine that allows selective-area scanning of the FPGA in order to increase the time available for reconfiguration without compromising reliability. A case study drawn from the NASA JPLs Compositional InfraRed Imaging Spectrometer (CIRIS) instrument shows a time saving of up to 74% over the Xilinx SEM IP when only the data processing core of the CIRIS instrument is considered.