Ali Ebrahim

Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems

This letter presents efficient and modular task scheduler and allocator support for dynamically and partially reconfigurable electronic systems. This enables hardware tasks to be preempted and arbitrarily placed at an optimal position on the chip on-the-fly. In particular, we present a novel fault-tolerant allocating algorithm called “best-fit empty area compact (BF-EAC),” and its on-chip implementation on a Xilinx Virtex-4 field-programmable gate array (FPGA), which circumvents emerging faults while maintaining more compact empty areas for emerging tasks. We also present an implementation of the early deadline first (EDF) scheduling heuristic used to optimize the chronological order of execution of hardware tasks to meet real time constraints. Put together, the placement and scheduling architecture efficiently exploits chip resources with a μs-grade computing speed and a lightweight footprint (less than 500 slices).

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined.

R3TOS-Based Autonomous Fault-Tolerant Systems

An autonomous fault-tolerant system (AFTS) is one that can reconfigure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain the original functionality. This capability makes an AFTS especially suitable for use in harsh environments, where traditional electronics technology is susceptible to failure. This article describes the contributions of the Reliable Reconfigurable Real-Time Operating System (R3TOS) for building an AFTS using currently available Xilinx partially-reconfigurable field-programmable gate arrays. Namely, this article discusses what R3TOS offers for developing durable, dependable, and real-time embedded systems to be used in rugged environments. In this context, the article presents an R3TOS-based inverter controller of a real-world railway traction system that is proven to recover from most of the errors injected without requiring any human intervention.

Novel dynamic partial reconfiguration implementation of k-means clustering on FPGAs: comparative results with GPPs and GPUs

K-means clustering has been widely used in processing large datasets in many fields of studies. Advancement in many data collection techniques has been generating enormous amounts of data, leaving scientists with the challenging task of processing them. Using General Purpose Processors (GPPs) to process large datasets may take a long time; therefore many acceleration methods have been proposed in the literature to speed up the processing of such large datasets. In this work, a parameterized implementation of the K-means clustering algorithm in Field Programmable Gate Array (FPGA) is presented and compared with previous FPGA implementation as well as recent implementations on Graphics Processing Units (GPUs) and GPPs. The proposed FPGA has higher performance in terms of speedup over previous GPP and GPU implementations (two orders and one order of magnitude, resp.). In addition, the FPGA implementation is more energy efficient than GPP and GPU (615x and 31x, resp.). Furthermore, three novel implementations of the K-means clustering based on dynamic partial reconfiguration (DPR) are presented offering high degree of flexibility to dynamically reconfigure the FPGA. The DPR implementations achieved speedups in reconfiguration time between 4x to 15x.

On enhancing the reliability of internal configuration controllers in FPGAs

In fault-tolerant FPGA systems, the internal reconfiguration capabilities supported in modern FPGAs is commonly utilized for enhanced fault mitigation. In such systems, faults in the internal configuration controller can degrade the fault-tolerance of the system and in extreme cases can lead to additional faults injected into the system. In this paper we present different methods for enhancing the reliability of internal configuration controllers in FPGAs. We demonstrate the design of a custom ICAP controller for Xilinx Virtex FPGAs and compare the reliability and area overhead for Triple Modular Redundancy (TMR), Dual Modular Redundancy (DMR) and Cyclic Redundancy Check (CRC) design schemes. We also evaluate the effectiveness of internal readback and external configuration memory scrubbing and show how a combination of the two methods can reduce the number of single points of failure in the system.

Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs

This paper addresses the high-performance systems which are based on swapping relocatable partial bitstreams (also called hardware tasks) in and out of an FPGA device using Dynamic Partial Reconfiguration (DPR) in Xilinx Virtex FPGAs. Configuration speed is important in such systems to achieve high performance. Previous research efforts were focused on over-clocking the Internal Configuration Access Port (ICAP) and compressing the partial bitstreams of the hardware tasks to enhance the configuration speed. We propose the use of the Multiple Frame Write (MFW) feature to significantly reduce the configuration time when multiple instances of a hardware task are needed. In this paper, we demonstrate the design and implementation of a novel internal reconfiguration engine which dynamically generates partial bitstreams required for simultaneous configuration of multiple clones of relocatable hardware tasks.

Online clock routing in Xilinx FPGAs for high-performance and reliability

In this paper, we report the design and implementation of a reconfigurable system that exploits regional clocking resources that exist in Xilinx Virtex-4 FPGAs for increased performance and, for the first time, enhanced reliability. Unlike previous approaches, our system is able to individually manage the regional clock buffers (BUFRs) to adjust the frequency delivered to each hardware task and to detect and recover from faults affecting the clock-tree on-the-fly. Towards this end, we propose global and regional clock multiplexers, named GCMUX and RCMUX respectively, which allow for switching to spare clocking resources whenever needed. These multiplexers are based on the inner programmable interconnection points of the FPGA, leading to zero area overheads.

A dynamic partial reconfiguration design for camera systems

The image-processing pipeline is the core part of any camera system including digital still cameras, camcorders, camera phones and video surveillance equipments. The image-processing pipeline consists of a number of processing stages that enhance the image or remove any effects that are caused by surrounding conditions. These stages are computationally intensive and need special requirements to meet the real time processing. This paper discusses the pipeline parts and presents a high-performance and cost-effective implementation of the pipeline on Field Programmable Gate Arrays (FPGAs) using Dynamic Partial Reconfiguration (DPR) feature to exploit the FPGA resources over time and space. The paper shows that the implemented system adds much of flexibility to camera systems by using a reconfigurable region. The system can use an unlimited number of image processing pipeline stages to process the images without the need of huge number of logic resources to fit all the stages. Moreover, the stages are not fixed in this system, they can be changed upon the users decision. The architecture is designed to process still images of size 1920×1080. Each stage could process a full frame within 7.25 ms. A fast configuration engine is designed and deployed in the system. The engine shows that it can outperform the engine provided with zynq SoC by three times. The overall throughput of the system reaches 250 Megapixel/s.

Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)

This article presents a new solution for easing the development of reconfigurable applications using Field-Programable Gate Arrays (FPGAs). Namely, our Reliable Reconfigurable Real-Time Operating System (R3TOS) provides OS-like support for partially reconfigurable FPGAs. Unlike related works, R3TOS is founded on the basis of resource reusability and computation ephemerality. It makes intensive use of reconfiguration at very fine FPGA granularity, keeping the logic resources used only while performing computation and releasing them as soon as it is completed. To achieve this goal, R3TOS goes beyond the traditional approach of using reconfigurable slots with fixed boundaries interconnected by means of a static communication infrastructure. Instead, R3TOS approaches a static route-free system where nearly everything is reconfigurable. The tasks are concatenated to form a computation chain through which partial results naturally flow, and data are exchanged among remotely located tasks using FPGA’s reconfiguration mechanism or by means of “removable” routing circuits. In this article, we describe the R3TOS microkernel architecture as well as its hardware abstraction services and programming interface. Notably, the article presents a set of novel circuits and mechanisms to overcome the limitations and exploit the opportunities of Xilinx reconfigurable technology in the scope of hardware multitasking and dependability.

Design and implementation of fault-tolerant soft processors on FPGAs

This paper presents a novel hardware mechanism to facilitate the design and implementation of soft processors on FPGAs using the Error-correcting code (ECC)-protected memory and Triple Modular Redundancy (TMR). Such techniques highly harden the fault tolerance of soft processors, especially their memories, which are the most radiation susceptible resources on FPGAs. This is demonstrated in the implementation of a fault-tolerant PicoBlaze processor on Xilinx FPGAs, in which we used an additional LookAhead technique to synchronize the processor with ECC-protected Block RAM (ECC BRAM). The resulting fault-tolerant PicoBlaze processor has the benefit of having a self-recoverable program memory in the presence of Single Error Upsets (SEUs), without halting the processor. Our techniques can be applied to other soft processors e.g. Xilinx MicroBlaze or Altera Nios.