Adib Kabir Chowdhury

Design and synthesis of reversible arithmetic and Logic Unit (ALU)

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Reversible logic gate implementation as switch controlled reversible full adder/subtractor

Reversible computation plays an important role in low power circuit design and efficient energy recycling. In this paper, a switch controlled efficient Reversible Full Adder/Subtractor (RFAS) is presented. RFAS block is further used in the construction of n-bit adder/subtractor. The proposed design is analyzed and compared against the existing reversible techniques. Features such as, hardware cost, logic calculation and gate count etc. are investigated to show the efficiency of the design. Simulation results are verified using Altera Quartus II and ModelSim software. Observations suggest that the circuit offers lesser hardware complexity compared to the existing reversible full adder.

Vision-based registration for augmented reality-a short survey

The purpose of this paper is to explore some existing techniques in vision-based registration for Augmented Reality (AR) and present them collectively. AR is a branch of computer vision which generally overlays Virtual Objects (VOs) on actual images of real-world scenes in order to provide additional information about the scene to the user. Due to its wide range of applications in the fields of medical, robotics and automotive, geographic and remote sensing, military and aerospace, it has gained high demand. In any AR system, registration is the key to make the augmented scene appearing natural. Registration process must avoid occlusion of VOs and objects in the real world and align the VOs precisely. Optics-based and video-based are two well-known industrial AR systems. Researchers show that even with a single camera model registration for an AR is plausible but, VOs may be registered in front of real-world objects. It is because the registration process lacks depth information of the scene. However, employing stereo vision system and utilizing available natural features in a real-world scene and set of arbitrary multiple planes one can improve accuracy of VO registration. Thus, an AR system becomes robust if it is devised with algorithms to extract and track natural features in real-time.

Design of full adder/subtractor using irreversible IG-A gate

In recent years, reversible computation has received much attention in the field of low power circuit design. In this paper, an irreversible IG-A gate is presented. The gate is further used to design irreversible full adder/subtractor (IAS). Furthermore, IAS block is utilized to construct n-bit adder and subtractor. Proposed IAS design is analyzed and compared against the existing reversible methods. Features such as, hardware cost, logic calculation and gate count are investigated to show the efficiency of the design. Transistor level design and simulation of IG-A circuit are shown using Cadence OrCAD Lite. The one-bit IAS simulation results are verified using Altera Quartus II and ModelSim software. Simulation results show that the circuit offers reduced hardware complexity as compared to the existing reversible full adder design.

An analysis of MVL neural operators using feed forward backpropagation: Realization and application of logic synthesis

In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize Multi-Valued Logic (MVL) functions. The algorithm is combined with back-propagation learning capability and MVL operators. The operators are used to synthesize the functions. Consequently the synthesized expressions are applied by the MVL neural operators. The advantages of NND-MVL algorithm are demonstrated by accuracy measurement of MVL neural operator realization. Furthermore, evaluation of NND-MVL algorithm is analyzed by its application, propagation delay and accuracy achieved for training with 4 hidden neurons. In a brief, an effort of training MVL neural operators and utilizing them for logic synthesis is observed.

Multiple Valued Logic (MVL) Approach: Network Congestion Management

Network congestion is one of the main concerns for the fast-developed computer science and communication industries. With the increasing amount of data transferred, existing network are congested leading to loss of data during the transmission process. This book proposes a new method to network congestion management using multi-valued logic as an approach. It also introduces the reduction logic operator and its application in managing network congestion.