Lenin Gopal

Design and synthesis of reversible arithmetic and Logic Unit (ALU)

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Design of reversible multiplexer/de-multiplexer

Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic logical functions such as AND, XOR, MUX etc. Besides these functions, other advantage of the proposed R-I gate is that it can be used as a 1:2 de-multiplexer without requiring any extra logic circuits and the proposed R-II gate can be used as a half adder circuit. The proposed reversible gates are implemented and verified using Xilinx ISE 10.1 software. The simulation results show that the proposed designs are more efficient in terms of gate count, garbage outputs and constant inputs than the existing reversible logic gate.

Reversible logic gate implementation as switch controlled reversible full adder/subtractor

Reversible computation plays an important role in low power circuit design and efficient energy recycling. In this paper, a switch controlled efficient Reversible Full Adder/Subtractor (RFAS) is presented. RFAS block is further used in the construction of n-bit adder/subtractor. The proposed design is analyzed and compared against the existing reversible techniques. Features such as, hardware cost, logic calculation and gate count etc. are investigated to show the efficiency of the design. Simulation results are verified using Altera Quartus II and ModelSim software. Observations suggest that the circuit offers lesser hardware complexity compared to the existing reversible full adder.

Joint MMSE transceiver design in non-regenerative MIMO relay systems with covariance feedback

In this paper, the problem of transceiver design in a non-regenerative MIMO relay system is addressed, where linear signal processing is applied at the relay and destination to minimize the mean-squared error (MSE) of the signal waveform estimation. The optimal structure of the relay precoding matrix is derived with the assumption that the relay knows the channel covariance information of the relay-destination link and the full channel state information (CSI) of the source-relay link. Simulation results demonstrate that the proposed scheme outperforms conventional relay algorithms, and its performance is comparable to the optimal relay algorithm using the full relay-destination CSI.

Designing and implementing a Wi-Fi enabled mobile robot

The demand for mobile reconnaissance robots has increased since the beginning of the 21st century war. The army mainly uses these robots for reconnaissance and gathering intelligence data without putting the personnel in danger. In this paper we present the design and implementation of Wi-Fi enabled mobile robot for distributed surveillance applications. The robot is built on a 4 wheel chassis, powered by a Linksys WRT54-GL residential router and an Atmel microcontroller. It is also equipped with an IP camera with added pan/tilt capabilities and on-board sensors which relays feedback information to the human operator. The software on the robot is programmed in C language and the Control Console is programmed in Java. In order to test the performance of the robot, the robot is tested under three scenarios, Indoor, Outdoor and Line of sight.

Design of an FPGA-based OFDM transceiver for DVB-T standard

The current communication systems tend to use OFDM systems in order to provide high data rates, minimize inter symbol interference and fading effect. Some examples are 802.11, 802.16, MC-CDMA, Digital Video Broadcasting (DVB), Wireless USB or Wireless Firmware among others. Trying to provide a solution to the new devices emerging, slow standard adoption, poor spectrum use, etc. This work presents an FPGA design, validation and implementation of an Orthogonal Frequency Division Multiplexing (OFDM) transceiver for DVB-T using a high level design tool and also reports the resources requirements for the presented system.

Tomlinson-Harashima Precoding Based Transceiver Design for MIMO Relay Systems With Channel Covariance Information

In this paper, we investigate the performance of the Tomlinson-Harashima (TH) precoder based nonlinear transceiver design for a nonregenerative multiple-input multiple-output (MIMO) relay system assuming that the full channel state information (CSI) of the source-relay link is known, while only the channel covariance information (CCI) of the relay-destination link is available at the relay node. We first derive the structure of the optimal TH precoding matrix and the source precoding matrix that minimize the mean-squared error (MSE) of the signal waveform estimation at the destination. Then we develop an iterative algorithm to optimize the relay precoding matrix. To reduce the computational complexity of the iterative algorithm, we propose a simplified precoding matrices design scheme. Numerical results show that the proposed precoding matrices design schemes have a better bit-error-rate performance than existing algorithms.

An analysis of MVL neural operators using feed forward backpropagation: Realization and application of logic synthesis

In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize Multi-Valued Logic (MVL) functions. The algorithm is combined with back-propagation learning capability and MVL operators. The operators are used to synthesize the functions. Consequently the synthesized expressions are applied by the MVL neural operators. The advantages of NND-MVL algorithm are demonstrated by accuracy measurement of MVL neural operator realization. Furthermore, evaluation of NND-MVL algorithm is analyzed by its application, propagation delay and accuracy achieved for training with 4 hidden neurons. In a brief, an effort of training MVL neural operators and utilizing them for logic synthesis is observed.

Channel covariance information based transceiver design for AF MIMO relay systems with direct link

In this paper, we propose a design scheme for amplify-and-forward multiple-input multiple-output (AF MIMO) relay system with direct link to minimize the mean-squared error (MSE) of the signal estimation at the destination. In the proposed design scheme, an optimal precoding matrix is derived with the assumption that the full channel state information (CSI) of the source-relay link and partial channel state information such as channel covariance information (CCI) of the relay-destination link are available at the relay. In practical cases, if the destination is closer to the source, the source-destination link cannot be ignored. Hence, in this paper, we assume that the relay knows the partial channel state information of the source-destination link. Based on this assumption, an iterative optimal covariance algorithm is developed to achieve the minimum MSE of the signal estimation at the destination. In order to reduce computational complexity of the proposed optimal covariance algorithm, a suboptimal covariance algorithm is proposed. A numerical example shows that the developed optimal covariance algorithm outperforms the conventional CCI based MSE algorithms.

Simplified robust design for nonregenerative ulticasting MIMO relay systems

In this paper, we propose a robust transceiver design for nonregenerative multicasting multiple-input multiple-output (MIMO) relay systems where a transmitter broadcasts common message to multiple receivers with aid of a relay node and the transmitter, relay and receivers are all equipped with multiple antennas. In the proposed design, the actual channel state information (CSI) is assumed as a Gaussian random matrix with the estimated CSI as the mean value, and the channel estimation errors are derived from the well-known Kronecker model. In the proposed design scheme, the transmitter and relay precoding matrices are jointly optimized to minimize the maximal mean squared-error (MSE) of the estimated signal at all receivers. The optimization problem is highly nonconvex in nature. Hence, we propose a low complexity solution by exploiting the optimal structure of the relay precoding matrix. Numerical simulations demonstrate the improved robustness of the proposed transceiver design algorithm against the CSI mismatch.