Aditya Agarwal

Efficient production of silicon-on-insulator films by co-implantation of He+ with H+

We have investigated the process of thin film separation by gas ion implantation and wafer bonding, as well as the more basic phenomenon of blistering, on which the technique is based. We show that when H and He gas implants are combined they produce a synergistic effect which enables thin-film separation at a much lower total implantation dose than that required for either H or He alone. By varying the H and He implantation doses we have been able to isolate the physical and chemical contributions of the gases to the blistering processes. We find that the essential role of H is to interact chemically with the implantation damage and create H-stabilized platelet-like defects, or microvoids. The efficiency of H in this action is linked to its effective lowering of the silicon internal surface energy. The second key component of the process is physical; it consists of diffusion of gas into the microvoids and gas expansion during annealing, which drives growth and the eventual intersection of the microvoids ...

MECHANISM FOR THE REDUCTION OF INTERSTITIAL SUPERSATURATIONS IN MEV-IMPLANTED SILICON

We demonstrate that the excess vacancies induced by a 1 MeV Si implant reduce the excess interstitials generated by a 40 keV Si implant during thermal annealing when these two implants are superimposed in silicon. It is shown that this previously observed reduction is dominated by vacancy annihilation and not by gettering to deeper interstitial-type extended defects. Interstitial supersaturations were measured using B doping superlattices (DSL) grown on a silicon-on-insulator (SOI) substrate. Implanting MeV and keV Si ions into the B DSL/SOI structure eliminated the B transient enhanced diffusion normally associated with the keV implant. The buried SiO2 layer in the SOI substrate isolates the deep interstitials-type extended defects of the MeV implant, thereby eliminating the possibility that these defects getter the interstitial excess induced by the keV Si implant.

DEPTH PROFILING OF VACANCY CLUSTERS IN MEV-IMPLANTED SI USING AU LABELING

A technique for profiling the clustered-vacancy region produced by high-energy ion implantation into silicon is described and tested. This technique takes advantage of the fact that metal impurities, such as Au, are trapped in the region of excess vacancies produced by MeV Si implants into silicon. In this work, the clustered-vacancy regions produced by 1-, 2-, and 8-MeV Si implants into silicon have been labeled with Au diffused in from the front surface at 750 °C. The trapped Au was profiled with Rutherford backscattering spectrometry. The dynamics of the clustered-vacancy region were monitored for isochronal annealing at 750–1000 °C, and for isothermal annealing at 950 °C, for 10–600 s. Cross-sectional transmission electron microscopy analysis revealed that after the drive-in anneal, the Au in the region of vacancy clusters is in the form of precipitates. The results demonstrate that the Au-labeling technique offers a convenient and potentially quantitative tool for depth profiling vacancies in clusters.

BORON-ENHANCED DIFFUSION OF BORON FROM ULTRALOW-ENERGY ION IMPLANTATION

We have investigated the diffusion enhancement mechanism of boron-enhanced diffusion (BED), wherein boron diffusivity is enhanced four to five times over the equilibrium diffusivity at 1050 °C in the proximity of a silicon layer containing a high boron concentration. It is demonstrated that BED is driven by excess interstitials injected from the high boron concentration layer during annealing. For evaporated layers, BED is observed above a threshold boron concentration between 1% and 10%, though it appears to be closer to 1% for B-implanted layers. For sub-keV B implants above the threshold, BED dominates over the contribution from transient-enhanced diffusion to junction depth. For 0.5 keV B, this threshold implantation dose lies between 3×1014 and 1×1015 cm−2. It is proposed that the excess interstitials responsible for BED are produced during the formation of a silicon boride phase in the high B concentration layers.

Boron-enhanced diffusion of boron: Physical mechanisms

Silicon layers containing B in excess of a few atomic percent create a supersaturation of Si self-interstitials in the underlying Si, resulting in enhanced diffusion of B in the substrate [boron-enhanced diffusion (BED)]. The temperature and time dependence of BED is investigated here. Evaporated boron as well as ultralow energy 0.5 keV B-implanted layers were annealed at temperatures from 1100 to 800 °C for times ranging from 3 to 3000 s. Isochronal 10 s anneals reveal that the BED effect increases with increasing temperature up to 1050 °C and then decreases. In contrast, simulations based on interstitial generation via the kick-out mechanism predict a decreasing dependence leading to the conclusion that the kick-out mechanism is not the dominant source of excess interstitials responsible for BED. The diffusivity enhancements from the combined effects of BED and transient-enhanced diffusion, measured in 2×1015 cm−2, 0.5 keV B-implanted samples, show a similar temperature dependence as seen for evaporated...

Transient enhanced diffusion after laser thermal processing of ion implanted silicon

The effect of laser thermal processing (LTP) on implantation-induced defect evolution and transient enhanced diffusion (TED) of boron was investigated. A 270-A-thick amorphous layer formed by 10 keV Si+ implantation was melted and regrown using a 20 ns ultraviolet laser pulse. Transmission electron microscopy revealed that recrystallization of the amorphous layer following LTP results in a high concentration of stacking faults and microtwins in the regrown region. Also, the end-of-range loop evolution during subsequent 750 °C furnace annealing, is different in a LTP sample compared to a control sample. Secondary ion mass spectroscopy of a boron marker layer 6000 A below the surface showed that LTP alone produced no enhanced diffusion. However, during subsequent furnace annealing, the boron layer in the LTP sample experienced just as much TED as in the control sample which was only implanted and furnace annealed. These results imply that laser melting and recrystallization of an implantation-induced amorph...

Ultra-shallow junction formation by spike annealing in a lamp-based or hot-walled rapid thermal annealing system: effect of ramp-up rate

Abstract Ultra-shallow p-type junction formation has been investigated using 1050°C spike anneals in lamp-based and hot-walled rapid thermal processing (RTP) systems. A spike anneal may be characterized by a fast ramp-up to temperature with only a fraction of a second soak-time at temperature. The effects of the ramp-up rate during a spike anneal on junction depth and sheet resistance were measured for rates of 40, 70 and 155°C/s in a lamp-based RTP, and for 50 and 85°C/s in a hot-walled RTP. B + implants of 0.5, 2 and 5 keV at doses of 2×10 14 and 2×10 15 cm −2 were annealed. A significant reduction in junction depth was observed at the highest ramp-up rate for the shallower 0.5-keV B implants, while only a marginal improvement was observed for 2- and 5-keV implants. It is concluded that high ramp-up rates can achieve the desired ultra-shallow junctions with low sheet resistance but only when used in combination with spike anneals and the lowest energy implants.

On the FinFET extension implant energy

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the I/sub off/-I/sub on/ performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current.

Ultra-Shallow Junctions by Ion Implantation and Rapid Thermal Annealing: Spike-Anneals, Ramp Rate Effects

Over the last couple of years rapid thermal annealing (RTA) equipment suppliers have been aggressively developing lamp-based furnaces capable of achieving ramp-up rates on the order of hundreds of degrees per second. One of the driving forces for adopting such a strategy was the experimental demonstration of 30nm p-type junctions by employing a ramp-up rate of ≈400°C/s. It was subsequently proposed that the ultra-fast temperature ramp-up was suppressing transient enhanced diffusion (TED) of boron which results from the interaction of the implantation damage with the dopant. The capability to achieve very high temperature ramp-rates was thus embraced as an essential requirement of the next generation of RTA equipment. In this paper, recent experimental data examining the effect of the ramp-up rate during spike-and soak-anneals on enhanced diffusion and shallow junction formation is reviewed. The advantage of increasing the ramp-up rate is found to be largest for the shallowest, 0.5-keV, B implants. At such ultra-low energies (ULE) the advantage arises from a reduction of the total thermal budget. Simulations reveal that a point of diminishing return is quickly reached when increasing the ramp-up rate since the ramp-down rate is in practice limited. At energies where TED dominates, a high ramp-up rate is only effective in minimizing diffusion if the implanted dose is sufficiently small so that the TED can be run out during the ramp-up portion of the anneal; for larger doses, a high ramp-up rate only serves to postpone the TED to the ramp-down duration of the anneal. However, even when TED is minimized at higher implant energies via high ramp-up rates, the advantage is unobservable due to the rather large as-implanted depth. It appears then that while spike anneals allow the activation of ULE-implanted dopants to be maximized while minimizing their diffusion the limitation imposed by the ramp-down rate compromises the advantage of very aggressive ramp-up rates.

Impact of extension implant energy purity and angle on the electrical characteristics of a 65nm device technology

We show that a significant fraction of the overlap in advanced logic technologies originates in the as-implanted dopant profile. As a consequence, small changes in the as-implanted profile have a large impact on device characteristics. We have developed a virtual, high-performance, planar, bulk, 65nm technology that we use as a platform to investigate the impact of imperfections in the extension implant stemming from (1) contamination of the beam with higher energy ions and (2) angular alignment of the incident ion beam to the wafer. We find that a deceleration ratio of 7 and an energy contamination equal to 1% of the total dose double the off current. Small (of the order 1°) beam steering of the incident beam as seen by the wafer leads to large changes in on current (of the order of 20%) and speed. Steering that results in shadowing of the source has a far larger impact than drain-side shadowing. This can be alleviated significantly by a quad implant, provided the tilt angle is sufficiently large, on the...