Hans-Joachim Ludwig Gossmann

Depth dependence of {311} defect dissolution

A deep band of {311} defects was created 520 nm below the silicon surface with a 350 keV Si implant followed by a cluster-forming rapid thermal anneal (800 °C, 1000 s). Chemical etching was used to vary the depth to the surface of the {311}-defect band. Afterwards, the defect dissolution was investigated at 750 °C for different times. Varying the depth in this fashion assures that only the depth and no other feature of the cluster distribution is changed. The {311} defects were analyzed by plan-view, transmission electron microscopy. We show that the dissolution time of the {311}-defect band varies linearly with depth, confirming that surface recombination controls the dissolution and is consistent with analogous observations of transient enhanced diffusion.

Ultra-shallow junction formation by spike annealing in a lamp-based or hot-walled rapid thermal annealing system: effect of ramp-up rate

Abstract Ultra-shallow p-type junction formation has been investigated using 1050°C spike anneals in lamp-based and hot-walled rapid thermal processing (RTP) systems. A spike anneal may be characterized by a fast ramp-up to temperature with only a fraction of a second soak-time at temperature. The effects of the ramp-up rate during a spike anneal on junction depth and sheet resistance were measured for rates of 40, 70 and 155°C/s in a lamp-based RTP, and for 50 and 85°C/s in a hot-walled RTP. B + implants of 0.5, 2 and 5 keV at doses of 2×10 14 and 2×10 15 cm −2 were annealed. A significant reduction in junction depth was observed at the highest ramp-up rate for the shallower 0.5-keV B implants, while only a marginal improvement was observed for 2- and 5-keV implants. It is concluded that high ramp-up rates can achieve the desired ultra-shallow junctions with low sheet resistance but only when used in combination with spike anneals and the lowest energy implants.

On the FinFET extension implant energy

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the I/sub off/-I/sub on/ performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current.

Junction formation and its device impact through the nodes: From single to coimplants, from beam line to plasma, from single ions to clusters, and from rapid thermal annealing to laser thermal processing

The fundamental design goals for a high-performance logic technology, maximizing speed while minimizing power, drive the design of the junctions and in turn the requirements on dopant placement and activation. In the early nodes implant energies of tens of keV and furnace anneals sufficed. Scaling into the deep submicron regime brought transient enhanced diffusion to the forefront and necessitated its control. This gave rise to rapid thermal annealing and low energy implants. The requirements of current high-performance logic technologies can only be satisfied with careful defect engineering and a further reduction in thermal budget at increased annealing temperatures: flash or laser annealing. Those almost diffusionless anneals make implant precision, such as angle control, imperative. Simultaneously, productivity requirements of implanters add molecular clusters to the list of implant species and lead for certain applications to a switch from beam line to plasma implantation.

Binding energy of vacancy clusters generated by high-energy ion implantation and annealing of silicon

We have measured the evolution of the excess-vacancy region created by a 2 MeV, 1016/cm2 Si implant in the silicon surface layer of silicon-on-insulator substrates. Free vacancy supersaturations were measured with Sb dopant diffusion markers during postimplant annealing at 700, 800, and 900 °C, while vacancy clusters were detected by Au labeling. We demonstrate that a large free vacancy supersaturation exists for short times, during the very early stages of annealing between the surface and the buried oxide (1 μm below). Afterwards, the free vacancy concentration returns to equilibrium in the presence of vacancy clusters. These vacancy clusters form at low temperatures and are stable to high temperatures, i.e., they have a low formation energy and high binding energy.

Impact of extension implant energy purity and angle on the electrical characteristics of a 65nm device technology

We show that a significant fraction of the overlap in advanced logic technologies originates in the as-implanted dopant profile. As a consequence, small changes in the as-implanted profile have a large impact on device characteristics. We have developed a virtual, high-performance, planar, bulk, 65nm technology that we use as a platform to investigate the impact of imperfections in the extension implant stemming from (1) contamination of the beam with higher energy ions and (2) angular alignment of the incident ion beam to the wafer. We find that a deceleration ratio of 7 and an energy contamination equal to 1% of the total dose double the off current. Small (of the order 1°) beam steering of the incident beam as seen by the wafer leads to large changes in on current (of the order of 20%) and speed. Steering that results in shadowing of the source has a far larger impact than drain-side shadowing. This can be alleviated significantly by a quad implant, provided the tilt angle is sufficiently large, on the...

Predictive process simulation of cryogenic implants for leading edge transistor design

Two cryogenic implant TCAD-modules have been developed: (i) A continuum-based compact model targeted towards a TCAD production environment calibrated against an extensive data-set for all common dopants. Ion-specific calibration parameters related to damage generation and dynamic annealing were used and resulted in excellent fits to the calibration data-set. (ii) A Kinetic Monte Carlo (kMC) model including the full time dependence of ion-exposure that a particular spot on the wafer experiences, as well as the resulting temperature vs. time profile of this spot. It was calibrated by adjusting damage generation and dynamic annealing parameters. The kMC simulations clearly demonstrate the importance of the time-structure of the beam for the amorphization process: Assuming an average dose-rate does not capture all of the physics and may lead to incorrect conclusions. The model enables optimization of the amorphization process through tool parameters such as scan speed or beam height.