Adrian G. Spencer

A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver

A low-IF polyphase channel filter for a dual-mode Bluetooth/Zigbee transceiver is described. Implemented in a standard 0.18-/spl mu/m CMOS process, the filter has a fifth-order 0.5-dB equiripple bandpass response and employs novel transconductor and preamplifier designs. It consumes /spl les/1 mW and achieves image band rejection /spl ges/44 dB, input referred noise of /spl les/52.2 /spl mu/Vrms and input referred third-order intermodulation intercept of /spl ges/20 dBVp, which gives a spurious-free dynamic range of /spl ges/68.4 dB. Chip area including its tuning circuit is 0.23 mm/sup 2/.

A Multirate Switched-Current Filter Using Class-AB Cascoded Memory

Switched-current (SI) techniques for modern short-range wireless filters are described. The cascoded Class-AB SI is employed for improved memory accuracy with minimum loss of overall performance. With emphasis on low power, a multirate SI scheme that features order reduction and simple interfacing of the continuous-time anti-alias filter to the sampled data SI filter is introduced. Implemented using a 3-V 0.35-mum digital CMOS process, the fifth-order complex bandpass SI filter was designed and optimized at 2.0-V supply voltage for Bluetooth application with 1-MHz center frequency and 1.2-MHz bandwidth. It has a voltage gain of 20.5 dB and achieves an image rejection of 45 dB, a spurious-free dynamic range of 64 dB and the signal-to-noise ratio of 67 dB

A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver [mobile phone applications]

A low-IF polyphase channel filter for a dual-mode Bluetooth/ZigBee transceiver is described. Implemented in a standard 0.18 /spl mu/m CMOS process, the filter has a fifth-order 0.5 dB equiripple bandpass response and employs novel transconductor and preamplifier designs. It consumes 1 mW and achieves image band rejection /spl ges/33 dB, signal-to-noise ratio of /spl ges/60 dB and input referred third-order intermodulation intercept of /spl ges/17 dBVp. Chip area, including its tuning circuit, is 0.23 mm/sup 2/.