John B. Hughes

Switched-currents : an analogue technique for digital technology

* Chapter 1: Introduction * Chapter 2: The Evolution of Analogue Sampled-Data Signal Processing * Basic Cells * Chapter 3: Switched-Current Architectures and Algorithms * Chapter 4: Switched-Current Limitations and Non-Ideal Behaviour * Chapter 5: Noise in Switched-Current Circuits * Chapter 6: Switched-Current Circuit Design Techniques * Chapter 7: Class AB Switched-Current Techniques * Filters * Chapter 8: Switched-Current Filters * Chapter 9: A Switched-Capacitor to Switched-Current Conversion Method * Chapter 10: Switched-Current Video Signal Processing * Chapter 11: Switched-Current Wave Analogue Filters * Data Converters * Chapter 12: Algorithmic and Pipelined A/D Converters * Chapter 13: High Resolution Algorithmic A/D Converters based on Dynamic Current Memories * Chapter 14: Building Blocks for Switched-Current Sigma-Delta Converters * Chapter 15: Continuous Calibration D/A Conversion * Other Applications * Chapter 16: Dynamic Current Mirrors * Chapter 17: Switched-Current Cellular Neural Networks for Image Processing * Analysis, Simulation and Test * Chapter 18: Test for Switched-Current Circuits * Chapter 19: Analysis of Switched-Current Filters * Chapter 20: Non-linear Behaviour of Switched-Current Memory Circuits * Future Directions * Chapter 21: GaAs MESFET Switched-Current Circuits * Chapter 22: Switched-Currents: State-of-the-Art and Future Directions

Circuit architectures for high linearity monolithic continuous-time filtering

Circuit architectures for high-linearity monolithic continuous-time filters are described based on the use of integrated passive components in active RC structures. Tunability of the frequency response is achieved by arranging either resistive or capacitive elements in programmable arrays. The array value is then set using a digital code produced by an on-chip calibration circuit. The advantages and disadvantages of possible configurations are analyzed, indicating the limits of usefulness. Different filter architectures are considered, and design equations for determining basic cell specifications are given. The analyses are compared with results of experimental integrated filter designs, confirming that both very high linearity (-90 dB) and reasonable tuning accuracy (around +or-5%) are achievable. >

High-linearity continuous-time filter in 5-V VLSI CMOS

High-linearity self-tuning continuous-time filters, fabricated in a standard 1.6- mu m 5-V CMOS process, are presented. Frequency control is achieved using switchable arrays of highly linear double-polysilicon capacitors in an active RC filter structure, resulting in tunable filters with very low signal distortion. One filter, a Tow-Thomas biquad, exhibits dynamic range and signal linearity of typically 91 dB. Another smaller implementation, a Sallen and Key filter, attains >or=76 dB. Cutoff frequency response is maintained to an accuracy of around +or-5%. >

A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver

A low-IF polyphase channel filter for a dual-mode Bluetooth/Zigbee transceiver is described. Implemented in a standard 0.18-/spl mu/m CMOS process, the filter has a fifth-order 0.5-dB equiripple bandpass response and employs novel transconductor and preamplifier designs. It consumes /spl les/1 mW and achieves image band rejection /spl ges/44 dB, input referred noise of /spl les/52.2 /spl mu/Vrms and input referred third-order intermodulation intercept of /spl ges/20 dBVp, which gives a spurious-free dynamic range of /spl ges/68.4 dB. Chip area including its tuning circuit is 0.23 mm/sup 2/.

Second generation switched-current signal processing

A switched-current integrator configuration with greatly improved sensitivity to transistor mismatch is described. Forward-Euler, backward-Euler, and bilinear-z mappings are described, as well as an integrator which responds to the derivative of the input current. An universal integrator configuration which performs an identical algorithm to a well-known switched-capacitor universal integrator is developed. It can be used to translate known switched-capacitor filter topologies into switched-current counterparts, as is demonstrated by the simulation of a sixth-order low-pass filter.<<ETX>>

S/sup 2/I: a two-step approach to switched-currents

The principal causes of nonideal behavior which degrade precision and linearity in switched-current circuits, and the circuit techniques which are frequently applied to suppress them, are reviewed. These techniques include the use of negative feedback to reduce errors resulting from channel-length modulation and capacitive feedback, and fully-differential circuits with charge cancellation to reduce switch charge injection. It is argued that this piecemeal application of circuit techniques to suppress individual errors frequently carries penalties for silicon area, power dissipation, bandwidth and low supply voltage operation. An alternative approach is presented which attempts to enhance basic cell performance through successive refinement of the memorized sample. This is achieved in a two-step technique, called S/sup 2/ I, in which the input sample is coarsely memorized, a process which introduces a combination of all the normal errors, followed by detection and suppression of the combined errors. The circuit solution requires the addition to the basic memory cell of only two extra switches. The new cell carries little or none of the aforementioned penalties.<<ETX>>

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS ICs fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S/sup 2/I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 /spl mu/m standard CMOS process, they demonstrate state-of-the-art performance.

A full Nyquist 15 MS/s 8-b differential switched-current A/D converter

An 8-bit 15MS/s A/D converter using a differential Switched-Current (SI) pipeline architecture is described. The architecture and circuit design are noteworthy in being optimised so that the converter maintains performance across the whole input Nyquist band. The converter is fabricated in a standard 0.8¿m 5V digital CMOS process and occupies 2.4mm2.

Switched-current system cells

Two styles of filter module, one based on the switched-current integrator and the other on the switched-current differentiator, are presented. Design methods for implementing filters with cascaded biquadratic sections using these modules are given. Two topologies for an elementary current memory cell having circuit properties advantageous to this design environment are described.<<ETX>>

A switched-current double sampling bilinear z-transform filter technique

A filter technique, based on an integrator/summer which performs the bilinear z-transform and achieves two samples per clock period, is described. The operation of the integrator/summer is analysed and this is supported by simulation. As an example, a 3rd order lowpass elliptic ladder filter is designed. Measurement of an IC designed for a cut-off frequency of 8 MHz with sampling at 80 MHz confirm the technique and indicate that operation at sample frequencies beyond 100 MHz is feasible.<<ETX>>