Adrian Maxim

A low jitter 125-1250 MHz process independent 0.18 /spl mu/m CMOS PLL based on a sample-reset loop filter

This low-jitter high-resolution ripple-pole-less process-independent 0.18/spl mu/m CMOS PLL is based on a sample-reset loop filter technique. The key feature of this architecture is elimination of phase detector frequency spurs due to the ICO control current spikes during input phase difference. This is accomplished by averaging the charge injected by the proportional path over an entire input update period. As a consequence, the ICO control current has a shape characterized by a staircase of low amplitude steps, versus one characterized by narrow high amplitude pulses, and needs much less filtering for low-jitter operation.

A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation

The aim of this paper is to present a new physical based SPICE model for the deep-submicron CMOS transistors mismatch. It starts from the well known Pelgroms area law and adds the second order effects specific to deep-submicron devices (lateral diffusion, charge sharing, channel doping fluctuation, mobility degradation, etc). The matching parameters are computed directly from the process parameters, and scaling down equations were developed and experimentally verified. The resulting matching model is independent of the SPICE level used for MOSFET modeling, being valid both for the simple Level 3 and the high complexity BSIM3 model. The model was experimentally verified for a wide range of CMOS processes (0.4 /spl mu/m, 0.35 /spl mu/m, 0.25 /spl mu/m and 0.18 /spl mu/m), showing a better accuracy in comparison with the existing matching models, that give significant errors when used for deep-submicron devices.

A novel power PIN diode behavioral SPICE macromodel including the forward and reverse recoveries and the self-heating process

This paper presents a new method of power PIN diodes SPICE macromodeling, based on the direct implementation of the physical based electrical and thermal device internal equations with nonlinear controlled voltage and current sources. In order to simulate the distributed effects of both the electrical and thermal phenomena within the device, the solutions of the ambipolar diffusion and heat diffusion equations were modeled with their irrational Laplace domain expressions. The electrical model of the PIN diode accurately simulates the conductivity modulation of the base region resistance, the emitter recombination effect and the forward and reverse recoveries and the thermal model simulates the device self-heating process. The new PIN diode SPICE macromodel is built-up only with nonlinear controlled voltage and current sources, low complexity SPICE devices, and thus leads to a high computational efficiency and low convergence problems. A key advantage of this macromodel is its portability to all the modern SPICE simulators that support the Analog Behavioral Macromodeling facilities. There were developed the behavioral macromodels for several power PIN diodes from different vendors and the simulation results show an excellent agreement with the data-sheets characteristics.

A unified high accuracy behavioral SPICE macromodel of operational amplifiers featuring the frequency, temperature and power supply influences and the Monte Carlo simulation

The aim of this paper is to present a new analog behavioral SPICE macromodeling technique of the operational amplifiers, based on a direct implementation of their time and frequency domain internal equations with nonlinear controlled voltage and current sources. It greatly increases the simulation accuracy by considering the high order poles and zeros of the differential and common mode gains, as well as of the input and output impedances. Also the macromodel includes the temperature dependencies of the main op amp electrical parameters and it considers their tolerances for the Monte Carlo simulation. The proposed behavioral macromodel is a unified one, valid for all the existing op amp technologies and it is portable easily in all the modern SPICE simulators that support the Analog Behavioral Macromodeling facilities. It is made only of passive elements and controlled sources, and thus it leads to a very low computation time, with no convergence problems. It uses directly the common data-sheets specifications as model parameters and thus eliminates the time consuming model calibration step.

A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics

This paper presents a new method of operational amplifiers SPICE macromodeling, based on a frequency domain description of the input-output transfer functions. It accurately models the frequency variations of the open-loop gain, the common-mode rejection, and the input and output impedances, by a direct specification of their Laplace domain expressions, with all theirs dominant poles and zeros. The temperature dependencies of the main OpAmps characteristics and the equivalent input noise are included. The proposed behavioral macromodel leads to a higher computational efficiency in comparison with the existing OpAmp SPICE models, with a higher accuracy and a better convergence.

High performance analog behavioral modeling of operational amplifiers

This paper presents a new method of operational amplifiers SPICE macromodeling, based on a frequency domain description of the input-output transfer functions. It accurately models the frequency variations of the open-loop gain, the common-mode rejection, and the input and output impedances, by a direct specification of their Laplace domain expressions with all theirs dominant poles and zeros. The temperature dependencies of the main opamp characteristics are also included. The proposed behavioral macromodel leads to a low analysis time in comparison with the other opamp methods of modeling, with a higher accuracy and a better convergence.

Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs

This paper presents a low jitter, high resolution frequency synthesizer realized in 0.18 /spl mu/m CMOS technology, using a novel sample-reset loop filter technique that gives a process independent damping factor, and low jitter operation with minimum ripple filtering pole requirements. PLL specifications include: operating range 125-1270 MHz, resolution <500 KHz, jitter <0.8%/spl middot/Tosc, and dissipating 75 mW from a 2.5 V supply.