Baker Scott

Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs

This paper presents a low jitter, high resolution frequency synthesizer realized in 0.18 /spl mu/m CMOS technology, using a novel sample-reset loop filter technique that gives a process independent damping factor, and low jitter operation with minimum ripple filtering pole requirements. PLL specifications include: operating range 125-1270 MHz, resolution <500 KHz, jitter <0.8%/spl middot/Tosc, and dissipating 75 mW from a 2.5 V supply.