Adrian Nunez

Analysis of subthreshold leakage reduction in CMOS digital circuits

Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques have been proposed that efficiently minimize this leakage power loss. A comprehensive survey and analysis of various subthreshold leakage power reduction techniques that are applicable to current battery operated devices is presented in this work with an emphasis on static CMOS circuits. Results show a clear tradeoff between leakage power and other circuit performance parameters. Based on this analysis, a designer or an automation tool would be able to select the appropriate leakage control technique for a particular application.

Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron

With the migration to deep sub-micron (DSM) process technologies, the static power (leakage) has become the major contributor to the designs overall power consumption. In this work, we show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We also present a high-level design/synthesis method, called power islands that minimize the leakage in the circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all the logic contained within it is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. A main benefit of power islands is the elimination of leakage in inactive components during the power down cycles of the islands, and hence a decrease in circuits power consumption. The effectiveness of the proposed technique is demonstrated through several examples implemented with 4 different feature sizes: 180 nm, 130 nm, 100 nm and 70 nm. These experiments showed improvements in leakage ranging from 41% to 80% at 70 nm due to power islands

Power islands: a high-level synthesis technique for reducing spurious switching activity and leakage

This work introduces a high-level synthesis (HLS) methodology that eliminates the spurious switching activity (SSA) and the leakage in a great portion of the resulting circuit through the use of power islands. A power island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all of the logic contained within it is idling. By powering down an island: (1) the spurious switching that results from the broadcast to idle components is silenced and (2) the power consumption due to leakage in inactive components are eliminated. Our experiments conducted on several synthesis benchmarks using a transistor-level simulator showed an average reduction of 11% in total power consumption due to the power islands without introducing any overhead. We can project that in future technologies, when leakage becomes a more dominant component of the overall power, significantly more savings can be gained from design with power islands

A novel methodology to reduce leakage power in CMOS complementary circuits

Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. The subthreshold leakage current increases exponentially in deep-submicron processes and hence is a crucial factor in scaling down designs. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, a novel technique that achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) for any CMOS complementary circuit is presented. It involves voltage balancing in the PUN and PDN paths using sleep transistors. Experimental results show significant leakage power savings (average of 54X at a temperature of 27oC) in CMOS circuits employing this sleep circuitry when compared to standard CMOS circuits. At any given temperature, using our methodology the leakage power loss increases linearly with increasing circuit complexity and hence the leakage loss can be predicted for any CMOS complementary circuit.

A tool to generate models based on behavioral IBIS models

Input/Output Buffer Information Specification (IBIS) behavioral models are widely used for circuit-level signal integrity (SI) analysis due to its fast simulation speed and good accuracy. This work presents a tool to generate models of circuits specified by IBIS models. The model generation tool estimates poles, rise time and fall time of a circuit specified by IBIS models. The method consists of two steps; first regression analysis is performed on IBIS data with Weibull distribution function (WCDF) as the regression function. Based on the estimated parameter values, rise time and fall time values are obtained. The second step involves matching moments of WCDF to circuit moments and obtaining the estimated poles of the system. The method is generic and is scalable in nanometer CMOS. CMOS inverters have been used to demonstrate the methodology.

A Novel Methodology To Reduce Leakage Power In Differential Cascode Voltage Switch Logic Circuits

Subthreshold leakage current increases exponentially in deep-submicron processes and hence is a crucial factor in scaling down designs. Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, a novel technique that achieves cancellation of leakage effects in both the pull-up transistor (PUT) as well as the pull-down network (PDN) paths of DCVSL circuits is presented. It involves voltage balancing in these paths using sleep transistors. Experimental results show significant leakage power savings (average of 61X at a temperature of 27deg C) in DCVSL circuits employing this sleep circuitry when compared to standard DCVSL circuits. At any given temperature, using our methodology the leakage power loss for DCVSL circuits is constant. A 4.31X improvement (on an average) in leakage savings using our methodology was observed when compared with the traditional power-gating technique

Pre-layout parasitic estimation in interconnects

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing

An automatic evaluation of phase noise on CMOS ring VCOs

The presence of phase noise in semiconductor devices can disturb the normal operation of analog and RF circuits. This paper presents a methodology to automatically evaluate the effects of phase noise in ring voltage controlled oscillators (VCOs). The methodology is based on SPICE circuit simulations and a mathematical analysis. A CAD tool was implemented and used to evaluate and optimize a four-stage ring VCO to show the effectiveness of the methodology