Nazanin Mansouri

Reliability-Centric High-Level Synthesis

The importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density circuits, and employment of power-saving techniques such as voltage scaling and component shut-down. As a result, it is becoming necessary to treat reliability as a first-class citizen in system design. In particular, reliability decisions taken early in system design can have significant benefits in terms of design quality. Motivated by this observation, this paper presents a reliability-centric high-level synthesis approach that addresses the soft error problem. The proposed approach tries to maximize reliability of the design while observing the bounds on area and performance, and makes use of our reliability characterization of hardware components such as adders and multipliers. We implemented the proposed approach, performed experiments with several designs, and compared the results with those obtained by a prior proposal.

Automated formal verification of scheduling process using finite state machines with datapath (FSMD)

This paper presents a methodology for the formal verification of scheduling during High-Level Synthesis(HLS). A notion of functional equivalence between two Finite State Machines with Datapath (FSMDs) is defined, on the basis of which we propose a methodology to verify scheduling. The functional equivalence between the behavioral specification and the scheduled Control-Data Flow Graph (CDFG) - that is the result of scheduling - is established using their FSMD models. The equivalence conditions are mathematically modeled and implemented in the higher-order specification language of theorem proving environment PVS, integrated with a HLS tool. The proof of correctness of the design is subsequently verified by the PVS proof checker.

An ILP formulation for reliability-oriented high-level synthesis

Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulation for reliability-oriented high-level synthesis that addresses the soft error problem. The proposed approach tries to maximize reliability of the design while observing the bounds on area and performance, and makes use of our reliability characterization of hardware components such as adders and multipliers. We implemented the proposed approach, performed experiments with several example designs, and compared the results with those obtained by a prior proposal. Our results show that incorporating reliability as a first-class metric during high-level synthesis brings significant improvements on the overall design reliability.

Reliability-centric hardware/software co-design

This paper proposes a reliability-centric hardware/software co-design framework. This framework operates with a component library that provides multiple alternates for a given task, each of which is potentially different from the others in terms of reliability, performance, and area metrics. The paper also presents an experimental evaluation of the proposed co-design framework using several example designs and a comparison to a conventional co-design method that does not consider reliability. Our experimental evaluation demonstrates that the proposed framework can be used to study the tradeoffs between area, performance, and reliability and that it is important to include reliability as a first class parameter in optimization.

Power Optimization With Power Islands Synthesis

With the migration to deep sub-micron process technologies, the power consumption of a circuit has come to the forefront of concerns, and as a result, the power has become a critical design parameter. This paper presents a novel high-level synthesis methodology, called Power Islands Synthesis, that eliminates the spurious switching activity and the leakage in a great portion of the resulting circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independently from the rest of the circuit and hence can be completely powered down when all of the logic it contains is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. By powering down an island during its idle cycles, the following occur: 1) The spurious switching that results from the broadcast to idle components is silenced and 2) the power consumption due to leakage in inactive components is eliminated. Experiments conducted on several synthesis benchmarks implemented at the layout level with a 65-nm process technology and simulated using a transistor-level simulator showed power savings ranging from 5% to 20% due to our methodology. The reported savings were entirely from the power down of combinational elements (functional resources) of the data path.

Automated formal verification of scheduling with speculative code motions

We present a methodology for formal verification of scheduling phase of High-Level Synthesis (HLS) when speculative code motions are performed during this process. Verification relies on establishing functional equivalence between the result of scheduling and the behavioral specification of the design, using their FSMD models. We propose and formally define a relation between the two FSMDs that is less constrained than the strong equivalence, but stronger than weak equivalence. For verification of scheduling involving speculative code motions, we propose the notion of FSMD recomposition, a transformation that alters the state sequence and/or the operation of each state, while maintaining the functionality. The equivalence conditions are formulated in higher-order logic, and their correctness is verified in the theorem proving environment PVS. The entire verification flow, including formal model extraction and proof generation is fully automated.

An ILP formulation for task scheduling on heterogeneous chip multiprocessors

One of the main difficuties to map an embedded application onto a multiprocessor architecture is that there are multiple ways of this mapping due to several constraints. In this paper, we present an Integer Linear Programming based framework that maps a given application (represented as a task graph) onto a Heterogeneous Chip Multiprocessor architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility. Our experimental results show that over 50% improvements on energy consumption are possible by using DVS, and the fully task duplicated schedules can be achieved under tight performance and energy bounds.

Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron

With the migration to deep sub-micron (DSM) process technologies, the static power (leakage) has become the major contributor to the designs overall power consumption. In this work, we show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We also present a high-level design/synthesis method, called power islands that minimize the leakage in the circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all the logic contained within it is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. A main benefit of power islands is the elimination of leakage in inactive components during the power down cycles of the islands, and hence a decrease in circuits power consumption. The effectiveness of the proposed technique is demonstrated through several examples implemented with 4 different feature sizes: 180 nm, 130 nm, 100 nm and 70 nm. These experiments showed improvements in leakage ranging from 41% to 80% at 70 nm due to power islands

Power islands: a high-level synthesis technique for reducing spurious switching activity and leakage

This work introduces a high-level synthesis (HLS) methodology that eliminates the spurious switching activity (SSA) and the leakage in a great portion of the resulting circuit through the use of power islands. A power island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all of the logic contained within it is idling. By powering down an island: (1) the spurious switching that results from the broadcast to idle components is silenced and (2) the power consumption due to leakage in inactive components are eliminated. Our experiments conducted on several synthesis benchmarks using a transistor-level simulator showed an average reduction of 11% in total power consumption due to the power islands without introducing any overhead. We can project that in future technologies, when leakage becomes a more dominant component of the overall power, significantly more savings can be gained from design with power islands

Enhancing scheduling solutions through ant colony optimization

In this paper a methodology based on ant colony optimization is presented to generate optimal scheduling during high-level synthesis. The classical force equation of the force-directed scheduling algorithm has been modified to accommodate the experiences accumulated by multiple agents in different iterations. In each iteration the obtained schedule is subjected to remaining steps of synthesis using standard techniques like clique partitioning for resource allocation and left edge algorithm. The results are used to improve scheduling in the next iteration.