Adrianus Willem Ludikhuize

A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications

A-BCD is a family of 100 V BCD processes on SOI offering latchup free operation, improved robustness, superior EMC performance, higher packing density, lower mask count, high temperature and higher frequency operation and easier design over bulk silicon technology. A wide range of a passive and active (5/12/25/60 and 100 V) devices are available. Device design tradeoffs for n- and p-type LDMOS and extended drain PMOS are discussed in detail. This and the low mask count makes it a versatile process for cost-sensitive consumer and automotive markets.

Switching performance of low-voltage N-channel trench MOSFETs

Guidelines for optimising the switching behaviour of low-voltage (LV) n-channel trench MOSFETs are presented, with emphasis on the geometry and the doping profile. In our optimisation we focussed on three parameters: the specific on-resistance (R/sub ds,on/), the gate-drain charge density (Q/sub gd/) and the off-state breakdown voltage. We obtained by simulations for the 30 V control switch an R/sub ds,on/ of less than 10 m/spl Omega/.mm/sup 2/ and an R/sub ds,on//spl middot/Q/sub gd/ of less than 15 m/spl Omega/.nC (applied voltage V/sub dd/=12 V). The result is a stripe cell structure with a trench width of 0.15 /spl mu/m, a cell pitch of 1.0 /spl mu/m. For the 25 V synchronous rectifier we obtained in the same feature size figures-of-merit of 5 m/spl Omega/.mm/sup 2/ and 17 m/spl Omega/.nC.

Applying DMOSTs, diodes and thyristors above and below substrate in thin-layer SOI

This paper reports on above- and below-substrate behavior of 120V LDMOSTs and on injecting bipolar-type devices like diodes, LIGBTs and thyristors, integrated in A-BCD thin-layer SOI technology. The full isolation as obtained in SOI allows for novel IC applications; an example is shown which generates an output swing from +110V to -110V.

Improved device ruggedness by floating buffer ring

An integrated low-substrate-leakage diode structure is considered, operated in reverse breakdown mode, having a parasitic npn transistor. At high current, the Kirk effect, causing shift of the potential by the space charge of moving carriers, leads to high electric fields and causes device degradation. The application of a protective n+ buffer ring around the cathode redistributes field and current and improves the ruggedness. This principle is also successfully applied for improved ESD performance of a lateral DMOST in a Silicon-on-Insulator process.

Extended (180 V) voltage in 0.6 /spl mu/m thin-layer-SOI A-BCD3 technology on 1 /spl mu/m BOX for display, automotive and consumer applications

In this paper the extension to 180 V of a compact 0.6 /spl mu/m Silicon-on-Insulator BCD-technology on 1 /spl mu/m Buried Oxide is discussed. DMOS performance (n- and p-type) at 180 V has been simulated after calibration on 120 V devices and first experimental results are given. Also the feasibility of milli-Ohm power devices in three level power metal without Cu plating is demonstrated.

Lateral 10-15 V DMOST with very low 6 mohm.mm/sup 2/ on-resistance

The paper reports a novel low-ohmic 6 m/spl Omega/.mm/sup 2/ LDMOS transistor with breakdown voltage of 15 V, above 10 V full operational voltage and R/sub on/*Q/sub gd/ (10 V/sub ds/)=11 m/spl Omega/.nC, integrated in a 0.6 /spl mu/m BCD IC process and suitable for power DC-DC converters from a 5-10 V supply.

Relation between robustness against ESD and against flash events in deflection amplifiers

Abstract We have investigated the relation between the electrostatic discharge (ESD) level achieved by vertical deflection amplifiers, used for television sets, and other discharge events affecting the reliability. In particular, it is known that the tubes of television sets sometimes produce so called flashes, which may damage the amplifiers. It is generally assumed that good ESD robustness corresponds to robustness against flash. However, we show that improving ESD performance can sometimes be detrimental to robustness against flash. We discuss the mechanism underlying these seemingly conflicting results and describe a method of improving ESD, while simultaneously enhancing flash robustness.