Anco Heringa

Novel power transistor design for a process independent high voltage option in standard CMOS

High voltage transistors can be implemented in standard CMOS by interleaving drain extensions with STI using the fine STI/active patterns. This approach facilitates integration of high voltage transistors in modern processes without increasing processing complexity. This paper presents an in depth analysis of simulation and experimental data in a commercial 90 nm CMOS process. It is shown that the STI layout in the channel and the drain extension can be optimised separately which results in a better current drive of the resulting voltage transistors. The scope and limits of this device concept are discussed

The dependence of the electro‐optic effect on electric field distribution and light beam propagation direction

A calculation of the electro‐optic effect in cubic materials is presented on the basis of Nelson’s perturbation approach and the calculated field distribution in an electro‐optic tip used for measurements in integrated circuits. In a strict sense, longitudinal electro‐optic sampling is not possible for this application, and it is found that the magnitude of the electro‐optic effect depends on both the field distribution and propagation direction of the light beam. This has important consequences for the interpretation of the signal amplitude obtained with longitudinal electro‐optic sampling. We show that the adverse effects can be circumvented in a configuration suitable for a null measurement.

On numerical problems in analytical calculations of extracellular fields in bounded cylindrical volume conductors

A method is presented for dealing with numerical problems in calculations of potential fields using expansions in modified Bessel functions. Using this method, problems in mathematical physics with cylindrical symmetry, e.g., volume conductor problems, can be solved with high accuracy.

Hot carrier degradation of HV-SOI devices under off-and on-state current conditions

Optimisation of High Voltage (HV) devices is typically governed by life-time considerations, most notably requirements for sufficient immunity against Hot Carrier Injection (HCI). Based on insight in the different degradation mechanisms in HV-SOI, we have identified distinctive acceleration methodologies for on- and off-state stress conditions.

Improved device ruggedness by floating buffer ring

An integrated low-substrate-leakage diode structure is considered, operated in reverse breakdown mode, having a parasitic npn transistor. At high current, the Kirk effect, causing shift of the potential by the space charge of moving carriers, leads to high electric fields and causes device degradation. The application of a protective n+ buffer ring around the cathode redistributes field and current and improves the ruggedness. This principle is also successfully applied for improved ESD performance of a lateral DMOST in a Silicon-on-Insulator process.