Adriel Ziesemer

Low-sensitivity to process variations aging sensor for automotive safety-critical applications

In this paper, circuit failure prediction by timing degradation is used to monitor semiconductor aging, which is a safety-critical problem in the automotive market. Reliability and variability issues are worsening with device scaling down. For safe operation, we propose on-chip, on-line aging monitoring. A novel aging sensor (to be selectively inserted in key locations in the design and to be activated from time to time) is proposed. The aging sensor is a programmable delay sensor, allowing decision-making for several degrees of severity in the aging process. It detects abnormal delays, regardless of their origin. Hence, it can uncover “normal” aging (namely, due to NBTI) and delay faults due to physical defects activated by long circuit operation. The proposed aging sensor has been optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Moreover, the area overhead of the new architecture is significantly less than the one of other aging sensors presented in the literature. Simulation results with a 65 nm sensor design are presented, ascertaining its usefulness and its low sensitivity, in particular to process variations.

Transistor level automatic layout generator for non-complementary CMOS cells

This paper presents a tool that makes it possible to generate full layouts of CMOS cells from its transistor level netlist in SPICE format. The tool generates the cells under a linear matrix (1I)) similar layout style and is able to support unrestricted circuit structures, continuous transistor sizing and folding. It features a transistor placement algorithm for width reduction that aims the reduction of the number of diffusion gaps and the wirelength of the internal connections. The circuit nets are routed using a negotiation-based algorithm, and an Integer Linear Programming (ILP) solver is used to compaction. The experimental results show that our methodology produces layouts competitive to exact methods. The runtimes were kept low even for cells with more than 30 transistors.

Predictive error detection by on-line aging monitoring

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on users requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

Built-in aging monitoring for safety-critical applications

Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is to monitor long-term performance degradation due to aging in such harsh environments. For safe operation, or for preventive maintenance, it is desirable that such monitoring may be performed on chip. On-line built-in aging sensors (activated from time to time) can be an adequate solution for this problem. The purpose of this paper is to present a novel methodology for electronic systems aging monitoring, and to introduce a new architecture for an aging sensor. Aging monitoring is carried out by observing the degrading timing response of the digital system. The proposed solution takes into account power supply voltage and temperature variations and allows several levels of failure prediction. Simulation results are presented, that ascertain the usefulness of the proposed methodology.

Automatic layout synthesis with ASTRAN applied to asynchronous cells

This work presents ASTRAN, a tool for automatic layout generation of cell libraries, and the use of this tool in the production of a cell library for asynchronous logic components called ASCEnD. In this context, ASTRAN is able to achieve orders of magnitude savings in cell generation time if compared to manual design. ASTRAN supports technologies down to 65nm and simultaneous two-dimensional cell layout compaction. It can deal with non-complementary logic cells, and allows producing any type of transistor network. The comparison of the generated layouts to those of the hand designed ASCEnD library revealed that ASTRAN achieves an average of 26% less area, about 50% less total parasitic capacitance and worst case input capacitance, and 23% lower delay.

An automated design methodology for layout generation targeting power leakage minimization

With the advent of deep sub-micron technologies, power consumption has become one of the most important research areas in microelectronics. This paper presents a design methodology for power leakage reduction in deep sub-micron digital circuits associated with an automated layout generator. The methodology consists of finding the channel length of transistors in the non-critical paths. The sizing algorithm is basically divided in two steps. First, transistors in the most non-critical paths are sized and then a refinement phase is employed. Different from the standard cell methodology, where several versions of each cell must be inserted in the library before synthesis, in our methodology the layout is generated after the channel length of transistors are defined. Results show that power leakage was reduced to 63% in a set of combinational benchmarks, without timing penalties.

A study on layout quality of automatic generated cells

Breaking-through algorithms have been proposed in the latest years enabling the new paradigm of library-free automatic layout synthesis. Library-free synthesis is known to achieve a huge reduction in the number of transistors required to implement a circuit, reducing leakage power consumption. On the other hand, automatic-generated cells are expected to have a larger area than designed-by-hand ones. In this paper we evaluate the layout quality of an automatic generated cell library by ASTRAN, showing that even reducing the set of cells to the ones available in a commercial cell library, the cells generated by our tool gives a better result than the library ones. Our experiments suggests that, although the automatic generated cells layout is less dense, therefore having larger cell areas, timing and power are similar and input capacitances are smaller. Those characteristics result in a design with a speed increased by 12% in average and with a 24% in average smaller power consumption in our test cases.

Automated Synthesis of Cell Libraries for Asynchronous Circuits

Asynchronous techniques are regaining relevance in the VLSI research community as they allow increasing robustness against process variability considerably, by relaxing timing assumptions. In addition, asynchronous circuits enable achieving low-power and high-speed designs. However, due to the absence of commercial dedicated standard cell libraries to take the most of asynchronous design, such circuits implementations are relegated to full-custom approaches only. This limits applicability of asynchronous solutions and avoids further development of dedicated design automation tools. This paper describes an improvement to this situation by proposing a fully-automated design-flow called ASCEnD-A, able to implement standard cells specifically required for asynchronous circuits design. The flow is capable of generating cells at the layout level, providing physical, power and timing models required by cell-based flows available in the state-of-the-art technologies.

Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN

This paper describes a technique to compact cell layouts efficiently using Mixed-Integer Linear Programming. By using binary variables we were able not only to model the conditional design rules, which apply to technology nodes down to 65nm, but also to compact layouts in the two-dimensions simultaneously. This technique was applied to a transistor network layout synthesis tool called ASTRAN which is being used to generate on-demand cells with unrestricted transistor network structure. We demonstrate in this paper that our technique is able to generate dense cell layouts, competitive with manually designed cells.

An Educational Tool for Design Automation of CMOS Cells

This paper presents a didactic tool that makes possible the automatic generation of full layouts of CMOS cells from its transistor level netlist in SPICE format. The tool allows the creation or modification of the netlist of a CMOS cell, including transistor sizing. It also let the user to quickly see the layout resulting after each modification. The tool does generate the cells in the linear matrix layout style and can automatically apply folding in the transistors when it is needed. Additionally, it is included a layout editor to allow the visualization of the generated layout.