Matheus T. Moreira

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques

The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-established design practices. Examples are the use of multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products. An alternative to overcome such problems is adopting Networks on Chip (NoCs) communication architectures supporting globally asynchronous locally synchronous (GALS) system design. This work proposes a GALS router with associated power control techniques, which enables low power SoC design. This is in contrast with previous works which centered attention in power reduction of SoC processing elements instead. The paper describes the asynchronous communication interface and the employed power control mechanism. The results obtained from simulation at the RTL level with timing show that, even when submitted to large rates of traffic injection, the proposed NoC displays a significant reduction in switching activity and consequently in power dissipation.

Impact of C-elements in asynchronous circuits

Asynchronous circuits are a potential solution to address some of the obstacles in deep submicron (DSM) design. One of the most frequently used devices to build asynchronous circuits is the C-element, a device present as a basic building block in several asynchronous design styles. This work measures the impact of three different C-element types. The paper compares the use of each implementation to build a real case asynchronous circuit, an RSA cryptographic core, and reports results of precise electrical simulations of each C-element. Findings in this work show that previous results in the literature about C-element implementation types must be re-evaluated when using C-elements in DSM technologies.

Blade -- A Timing Violation Resilient Asynchronous Template

Resilient designs offer the promise to remove increasingly large margins due to process, voltage, and temperature variations and take advantage of average-case data. However, proposed synchronous resilient schemes have either suffered from metastability or require modifying the architecture to add replay-based logic that recovers from timing errors, which leads to high timing error penalties and poses a design challenge in modern processors. This paper presents an asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. The template is supported by an automated design flow that synthesizes synchronous RTL designs to gate-level asynchronous Blade designs. The benefits of this flow are illustrated on Plasma, a 3-stage Open Core MIPS CPU. Our results demonstrate that a nominal area overhead of the asynchronous template of less than 10% leads to a 19% performance boost over the synchronous design due to average-case data and a 30-40% improvement when synchronous PVT margins are considered.

A 65nm standard cell set and flow dedicated to automated asynchronous circuits design

This work proposes a new design flow for rapid creation and characterization of standard cell sets for asynchronous design. The flow is fully automated except for the cell layout generation step. It has been applied to the design of a standard cell set supporting the Teak asynchronous synthesis tool. Cells use a 65 nm gate length commercial CMOS process. An asynchronous RSA cryptography circuit provides the design flow validation.

Adapting a C-element design flow for low power

The interest in non-synchronous design of digital circuits is growing due to technology scaling into deep submicron transistor geometries and to the problems this scaling causes to keep synchronous design advantageous. To enable most non-synchronous styles, the C-element is a fundamental device that has to be available as logic primitive. A recently proposed design flow improved a standard cell library, adding to it a set of typical asynchronous cells. However, the original flow did not address low power cells explicitly, which is a requirement in many modern applications. This paper proposes the extension of the flow so that it can expand the cell set with low power components. To achieve this, the paper adds a new degree of freedom to cell design. The new standard cell set encompasses over 500 different C-element implementations. The cell set employs a 65nm commercial CMOS process and is fully compliant with the foundry standard cell library. A fully asynchronous RSA crypto core was designed with the new cells, producing savings of more than 35% in total power and more than 69% in leakage power.

Design of NCL gates with the ASCEnD flow

Silicon technologies advances brought the possibility of integrating billions of transistors in a die. However, as transistors get smaller, some of the aspects that were negligible in previous technologies emerge as difficulties for the design in current and future technology nodes. In this context, fully synchronous circuits are harder to be built, as timing closure constraints become difficult to be met, and the asynchronous paradigm gains interest in the research community for its ability to cope with current technologies issues. AS-CEnD was proposed as a standard cell library for supporting standard-cell based design of asynchronous circuits and comprises a design flow for asynchronous components. This work presents the use of the ASCEnD flow to design NCL gates, which enable design improvement opportunities for some asynchronous templates. A total of 14 different NCL gates were designed at the layout level and had their electrical behavior characterized. As a result, electrical and physical models of these gates are now part of the ASCEnD library.

Automatic layout synthesis with ASTRAN applied to asynchronous cells

This work presents ASTRAN, a tool for automatic layout generation of cell libraries, and the use of this tool in the production of a cell library for asynchronous logic components called ASCEnD. In this context, ASTRAN is able to achieve orders of magnitude savings in cell generation time if compared to manual design. ASTRAN supports technologies down to 65nm and simultaneous two-dimensional cell layout compaction. It can deal with non-complementary logic cells, and allows producing any type of transistor network. The comparison of the generated layouts to those of the hand designed ASCEnD library revealed that ASTRAN achieves an average of 26% less area, about 50% less total parasitic capacitance and worst case input capacitance, and 23% lower delay.

Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy

Communication plays a crucial role in the design of high performance Multiprocessor Systems-on-Chip (MPSoC). Accordingly, Networks-on-Chip (NoC) have been successfully employed as a solution to deal with communication in complex MPSoCs. NoC-based architectures are characterized by various tradeoffs related to structural characteristics, performance specifications, and application demands. In new technologies, the relative values of wire delays and power consumption are increasing as the number of cores in 2D chips increase. The recent 3D IC technology applied to NoC architectures allows greater device integration and shorter interconnection links, which directly influences the communication performance. Through-Silicon Vias (TSVs) are used for the interconnection between vertical layers of a 3D IC. The drawback is that TSVs are usually very expensive in terms of silicon area, limiting their usage. This work explores the serialization of vertical links, employing a TSV multiplexing scheme for Lasio, a 3D mesh NoC. We implemented and analyzed the impact in network and application latency and in the occupancy of input buffers for a 4×4×4 mesh NoC with different multiplexing degrees, which imply different levels of TSV usage reduction and serialization. Results demonstrate that the proposed scheme allows reducing TSV usage with low performance overhead, pointing to potential benefits of the scheme in 3D NoC-based MPSoCs.

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing

This work presents the architecture and ASIC implementation of Hermes-AA, a flexible fully asynchronous network on chip router employing an adaptive routing algorithm. Hermes-AA enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specifically developed library of standard cell components. Area and timing characteristics for 65nm technology attest the quality of the design, which displays a maximum aggregated throughput of 7.75 Gbits/s

Hermes-a - an asynchronous NoC router with distributed routing

This work presents the architecture and ASIC implementation of Hermes-A, an asynchronous network on chip router. Hermes-A is coupled to a network interface that enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specific library of components. Area and timing characteristics for 180nm technology attest the quality of the design, which displays a maximum throughput of 3.6 Gbits/s.