Advait Madhavan

Race logic: a hardware acceleration for dynamic programming algorithms

We propose a novel computing approach, dubbed “Race Logic”, in which information, instead of being represented as logic levels, as is done in conventional logic, is represented as a timing delay. Under this new information representation, computations can be performed by observing the relative propagation times of signals injected into the circuit (i.e. the outcome of races). Race Logic is especially suited for solving problems related to the traversal of directed acyclic graphs commonly used in dynamic programming algorithms. The main advantage of this novel approach is that information processing (min-max and addition operations) can be very efficiently expressed through the manipulation of the natural delay chaining inherent to digital designs, which then results in superior latency, throughput, and energy efficiency. To verify this hypothesis, we designed several Race Logic implementations of a DNA global sequence alignment engine and compared it to the state-of-the-art conventional systolic array implementation. Our synthesized design shows that synchronous Race Logic is up to 4× faster when both approaches are mapped to a 0.5μm CMOS standard cell technology. At the same time the throughput for sequence matching per circuit area is about 3× higher at 5× lower power density for 20-long-symbol DNA sequences.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A configurable CMOS memory platform for 3D-integrated memristors

Memristors are emerging as powerful nanoscale devices for diverse applications, such as high-density memories and neuromorphic applications. However, this nascent technology requires considerable advancement before this vision is realized. We present a highly configurable CMOS interface chip which enables the characterization of on-chip memristors, especially for memory applications. The chip was fabricated in On-Semi 3M2P 0.5 μm occupying 2×2 mm2. The chip design allows for post-CMOS fabrication of memristors. The interface between the memristor and the CMOS circuitry was provided via a top metal contact. The chip was designed to support an area-distributed interface decoupling CMOS pitch and memristor pitch, enabling high-density memristor integration. Measurement results on post-CMOS fabricated Ag/SiO2/Pt memristive devices are reported. Though we have shown the results from one memristive material stack, thorough chip characterization demonstrates the versatility of the chip enabling its use with a wide variety of materials stacks.

Vertical integration of memristors onto foundry CMOS dies using wafer-scale integration

As Moores law scaling approaches its physical limit, there is increased interest in memristors as a replacement to transistors in memory applications due to their smaller footprint and superior scaling characteristics. However, memristors are intrinsically two-terminal devices, requiring an underlying CMOS control interface for proper operation. Thus the integration of CMOS and memristors is essential to the development of memristor technology. Accordingly, hybrid configurations have been proposed that make use of the advantages of CMOS while utilizing a high density of memristors. However, memristor/CMOS hybrid fabrication is not trivial because high-density memories require memristor dimensions to be much smaller than those of the underlying CMOS. Additionally, memristors typically make use of materials not allowed in conventional CMOS fabrication. These issues point to a post-CMOS fabrication approach. An associated consideration for memristor/CMOS hybrid fabrication is the high cost of whole wafer fabrication. While whole wafer fabrication of memristors is viable for large volume markets, it is not a practical route for niche applications or research. While this suggests the use of CMOS dies, edge effects typically set the minimum processable die size, as in the case of edge beads, which limit the achievable resolution of devices. To address these issues, we present a hybrid integration approach for post-CMOS vertical integration of memristors that is independent of CMOS die size. Our approach enables the vertical integration of memristors with small foundry-fabricated dies using a waferscale integration scheme. We demonstrate this approach using a 2.2-mm × 3.2-mm CMOS die fabricated in a standard dualpoly, three-metal 0.5-μm technology process. We use solution-processed BCB as an adhesive to embed CMOS dies into silicon wafer handles, allowing for easy handling and compatibility with a variety of lithography techniques such as electron-beam, nanoimprint and photolithography. The process is compatible with spin-coated planarization layers, such as polyimide or BCB, if nanometer-scale roughness is desired. As a demonstration, vertically integrated Ag/SiO2/Pt switches were fabricated on CMOS using conventional photolithography techniques in a university cleanroom and tested through the CMOS circuitry. The measurements were compared to those of Ag/SiO2/Pt switches fabricated off-chip in a similar process and indicate that the memristor/CMOS hybrids were fully functional. We believe this hybrid approach will pave the way for hybrid CMOS-memristor chips, enabling applications from neuromorphic computing to high-density memories.

Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits

A simple two-terminal memristive device has excellent scaling properties. For example, devices with footprint below 10×10 nm2 have been recently demonstrated and crossbar structures provide means of sustaining memristor density in large-scale circuits. While taking advantage of high density memristive devices is relatively straightforward in crossbar memory circuits, doing so efficiently in digital logic circuits still remains challenging. For example, only a small fraction (less than 1% on average) of memristive devices is actively utilized, i.e. turned to highly conductive state, in CMOL FPGA circuits which are configured to implement representative benchmark circuits. The main contribution of this paper is to demonstrate that such utilization can be much higher, more than 12%, in certain variety of CMOL FPGA circuits which are specifically designed for high throughput processing of streaming data. The high memristor device utilization is demonstrated by performing detailed mapping of network and image processing tasks and is mainly due to efficient use of high fan-in logic gates implementing exact and approximate pattern matching operations with streaming data. As a result of high utilization proposed circuits are estimated to have much higher computational throughput as compared to traditional approaches and represent a killer application which capitalizes efficiently on the density advantages of memristive devices.

Energy efficient computation with asynchronous races

By encoding information as digital signal propagation delay, rather than conventional logic levels, some basic processing operations become exceedingly energy efficient to implement. The result of such a computation can then be observed by relative timing differences between injected signals. We demonstrate the embodiment of such an approach utilizing current starved inverters as delay elements and characterize application-level artifacts of circuit-level variance. Specifically we chose the well-studied DNA sequence alignment problem for comparison and we show that, for the synthesized design, asynchronous races are 10x more energy efficient and 4x denser at comparable speeds as compared to prior approaches.

Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation

This article proposes a novel computing approach, dubbed race logic, in which information, instead of being represented as logic levels (as in conventional logic), is represented as a timing delay. Under this new representation, computations are based on the observation of the relative propagation times of signals injected into the circuit (that is, the outcome of races). Race logic is especially suited for solving problems related to the traversal of directed acyclic graphs commonly used in dynamic programming algorithms. The main advantage of this novel approach is that information processing (min-max and addition operations) can be efficiently expressed through the manipulation of the natural delay chaining inherent to digital designs, which then results in superior latency, throughput, and energy efficiency. To verify this hypothesis, the authors designed several race logic implementations of a DNA global sequence alignment engine and compared them to a state-of-the-art conventional systolic array implementation. The synthesized design shows that synchronous race logic is up to 4x faster when both approaches are mapped to 0.5-micron CMOS standard cell technology. At the same time, the throughput for sequence matching per circuit area is about 3x higher at 5x lower power density for 20-long-symbol DNA sequences.

3D ReRAM arrays and crossbars: Fabrication, characterization and applications

As the rapid progress of memristor technology continues, multi-layer stacking of these crossbars is needed in order to maximize the use of vertical space and achieve the required density for high throughput applications. This work summarizes our efforts of designing and building three-dimensional monolithically integrated memristive arrays and crossbars, both standalone and onto CMOS chips. We discuss the fabrication and electrical characterization details of stand-alone and CMOS integrated ReRAM arrays and crossbars together with their use in experimental demonstrations of digital and analog applications such as three-dimensional stateful logic, hardware security primitives and dot-product operations.

A 4-mm 2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions

We have fabricated and successfully tested, for the first time, a prototype chip of a Race Logic computing paradigm, which makes positive use of race conditions for accelerating a broad class of optimization problems, such as ones solved by dynamic programming algorithms. In Race Logic, information is encoded in signal propagation delay, rather than conventional logic levels, and the result of the computation is observed from relative timing differences between injected signals, i.e. the outcome of races. The 2×2 mm2 chip, fabricated in standard 180-nm CMOS technology, is designed to perform real-world DNA sequence alignment. Measurement results on typical benchmark data show 15 GCUPS sustained throughput at 70 mW power consumption, with only ∼ 15 mW spent for actual computation. These numbers compare very favorably with the state-of-the-art implementations.

Corrigendum: A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

This corrects the article DOI: 10.1038/srep42429.