Luke Theogarajan

Minimally Invasive Retinal Prosthesis

A wireless retinal implant with a low-power area-efficient stimulator chip features an ASK demodulator, single-ended-to-differential converter, low-power DLL and programmable current drivers. The chip dissipates 1.3mW from plusmn2.5V at a data rate of 100kb/s. The chip is powered and driven through a wireless inductive link separated by 15mm

A Low-Power Fully Implantable 15-Channel Retinal Stimulator Chip

Retinal prostheses are being developed around the world in hopes of restoring useful vision for patients suffering from certain types of diseases like age-related macular degeneration (AMD) and retinitis pigmentosa. The central component of an electrical retinal prosthesis is a wirelessly powered and driven stimulator chip. The chip receives commands from the outside and outputs biphasic current pulses to an electrode array placed in the retina that stimulate the remaining retinal neurons. The chip contains 30\thinspace000 transistors in a 0.5 mum technology (two-poly three-metal, 2P3M), occupies an area of 2.3 mm x 2.3 mm, and excluding the current sources consumes less than 2 mW of power. The chip is powered inductively via a 125 kHz power signal which is rectified to generate a plusmn2.5 V supply. The data signal is transmitted as an amplitude shift keyed (ASK) signal on a 13.56 MHz carrier. The data rate can be varied from 25 to 714 kHz and the symbol (0 or 1) is encoded as the pulse width of the data signal. A self-biased feedback-loop-based single-to-differential converter restores the signal to full rail levels. Clock and data recovery is performed by a self-biased low-power inverter-based delay-locked loop (DLL). The chip can receive four commands, and each command is 16 bits long. The current amplitude, pulse duration, and inter-pulse duration can be programmed by using the four commands.

A Hermetic Wireless Subretinal Neurostimulator for Vision Prostheses

A miniaturized, hermetically encased, wirelessly operated retinal prosthesis has been developed for preclinical studies in the Yucatan minipig, and includes several design improvements over our previously reported device. The prosthesis attaches conformally to the outside of the eye and electrically drives a microfabricated thin-film polyimide array of sputtered iridium oxide film electrodes. This array is implanted into the subretinal space using a customized ab externo surgical technique. The implanted device includes a hermetic titanium case containing a 15-channel stimulator chip and discrete circuit components. Feedthroughs in the case connect the stimulator chip to secondary power and data receiving coils on the eye and to the electrode array under the retina. Long-term in vitro pulse testing of the electrodes projected a lifetime consistent with typical devices in industry. The final assembly was tested in vitro to verify wireless operation of the system in physiological saline using a custom RF transmitter and primary coils. Stimulation pulse strength, duration, and frequency were programmed wirelessly from a Peripheral Component Interconnect eXtensions for Instrumentation (PXI) computer. Operation of the retinal implant has been verified in two pigs for up to five and a half months by detecting stimulus artifacts generated by the implanted device.

Realization of a 15-channel, hermetically-encased wireless subretinal prosthesis for the blind

A miniaturized, hermetically-encased, wirelessly-operated retinal prosthesis has been developed for implantation and pre-clinical studies in Yucatan mini-pig animal models. The prosthesis conforms to the eye and drives a microfabricated polyimide stimulating electrode array with sputtered iridium oxide electrodes. This array is implanted in the subretinal space using a specially-designed ab externo surgical technique that affixes the bulk of the prosthesis to the surface of the sclera. The implanted device includes a hermetic titanium case containing a 15-channel stimulator chip and discrete power supply components. Feedthroughs from the case connect to secondary power- and data-receiving coils. In addition, long-term in vitro pulse testing was performed on the electrodes to ensure their stability for the long lifetime of the hermetic case. The final assembly was tested in vitro to verify wireless operation of the system in biological saline using a custom RF transmitter circuit and primary coils. Stimulation pulse strength, duration and frequency were programmed wirelessly using a custom graphical user interface. Operation of the retinal implant has been verified in vivo in one pig for more than three months by measuring stimulus artifacts on the eye surface using a contact lens electrode.

Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management

Local thermal hot-spots in microprocessors lead to worst-case provisioning of global cooling resources, especially in large-scale systems where cooling power can be 50~100% of IT power. Further, the efficiency of cooling solutions degrade non-linearly with supply temperature. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots. Applying current to a superlattice TEC-film that is deposited between silicon and the heat spreader results in a Peltier effect, which spreads the heat and lowers the temperature of the hot-spot significantly and improves chip reliability. In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power. In order to quantify the potential power savings from using TECs in data center servers, we present a detailed power model that integrates on-chip dynamic and leakage power sources, heat diffusion through the entire chip, TEC and global cooler efficiencies, and all their mutual interactions. Our multi-scale analysis shows that, for a typical data center, TECs allow global coolers to operate at higher temperatures without degrading chip lifetime, and thus save ~27% cooling power on average while providing the same processor reliability as a data center running at 288K.

Opportunities and Challenges of Using Plasmonic Components in Nanophotonic Architectures

Nanophotonic architectures have recently been proposed as a path to providing low latency, high bandwidth network-on-chips. These proposals have primarily been based on micro-ring resonator modulators which, while capable of operating at tremendous speed, are known to have both a high manufacturing induced variability and a high degree of temperature dependence. The most common solution to these two problems is to introduce small heaters to control the temperature of the ring directly, which can significantly reduce overall power efficiency. In this paper, we introduce plasmonics as a complementary technology. While plasmonic devices have several important advantages, they come with their own new set of restrictions, including propagation loss and lack of wave division multiplexing (WDM) support. To overcome these challenges we propose a new hybrid photonic/plasmonic channel that can support WDM through the use of photonic micro-ring resonators as variation tolerant passive filters. Our aim is to exploit the best of both technologies: wave-guiding of photonics, and modulating using plasmonics. This channel provides moderate bandwidth with distance independent power consumption and a higher degree of temperature and process variation tolerance. We describe the state of plasmonics research, present architecturally-useful models of many of the most important devices, explore new ways in which the limitations of the technology can most readily be minimized, and quantify the applicability of these novel hybrid schemes across a variety of interconnect strategies. Our link-level analysis shows that the hybrid channel can save from 28% to 45% of total channel energy-cost per bit depending on process variation conditions.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

This paper presents a novel technique for the integration of small complementary metal-oxide semiconductor (CMOS) chips into a large area substrate. A key component of the technique is the CMOS chip-based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 μm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for microelectromechanical systems micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI Semiconductors 0.5 μm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 and 0.5 μm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. A CMOS/microfluidic hybrid system is also demonstrated based on the proposed integration technology.

Photonic Switching for Data Center Applications

Switching fabrics in data centers that rely on traditional electrical switches face scaling issues in terms of power consumption. Fast optical switches based on a silicon photonics platform can enable the high port speed and high interconnection density needed while still maintaining a small footprint and low power consumption.

Strategies for restoring vision to the blind: current and emerging technologies

This paper reviews the current state of the art in the design of retinal prostheses that hope to restore vision to the blind. The progress and the challenges faced by electronic implants are discussed. Additionally, the emerging technologies in the field are also reviewed. These include optogenetics and chemical interfaces that interface to the neural system. These emerging fields have made tremendous progress in the last few years and offer new hope in the design of retinal prosthetic devices.

A micropower delta-sigma modulator based on a self-biased super inverter for neural recording systems

This paper presents a micropower, supply scalable 2nd order delta-sigma modulator based on a novel self-biased fully differential super inverter for neural recording systems. By employing an enhanced cascode stage and complementary source degeneration, the super inverter achieves 52 dB of differential-mode gain and 42 dB of common-mode rejection ratio, while remaining self-biased at the optimum operating point. The prototype modulator is implemented in a 0.13 µm CMOS process and occupies 0.03 mm2 chip area. The fabricated IC achieves 66 dB SNR and 62 dB SNDR over the neural signal bandwidth of 8 KHz, while consuming 20 µW from 1.5 V supply. At 1.2 V supply, it achieves 67 dB SNR and 56 dB SNDR, with only 4.8 µW power consumption. The super inverter-based design methodology can be extended to other low power, high speed, and variation tolerant switched-capacitor circuits.